LHF00L13 Sharp Microelectronics, LHF00L13 Datasheet
LHF00L13
Specifications of LHF00L13
Related parts for LHF00L13
LHF00L13 Summary of contents
Page 1
... P S RODUCT PECIFICATIONS LHF00L13 Flash Memory (Model No.: LHF100L13) Issue Date: March16, 2004 ® 32M (2MB × 16) Spec No.: EL163054 Integrated Circuits Group ...
Page 2
...
Page 3
... Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. • Please direct all queries regarding the products covered herein to a sales representative of the company. LHF00L13 Rev. 2.45 ...
Page 4
... Command Definitions ................................................ 9 Functions of Block Lock and Block Lock-Down...... 11 Block Locking State Transitions upon Command Write........................................ 11 Block Locking State Transitions upon WP# Transition........................................ 12 Status Register Definition......................................... 13 LHF00L13 CONTENTS PAGE 1 Electrical Specifications ........................................ 14 1.1 Absolute Maximum Ratings........................... 14 1.2 Operating Conditions ..................................... 14 1.2.1 Capacitance.............................................. 15 1.2.2 AC Input/Output Test Conditions............ 15 1 ...
Page 5
... Special OTP (One Time Program) block provides an area to store permanent code such as an unique number. * ETOX is a trademark of Intel Corporation. LHF00L13 LHF00L13 32Mbit (2Mbit×16) Flash MEMORY Enhanced Data Protection Features • Individual Block Lock and Block Lock-Down with Zero-Latency • ...
Page 6
... WE# 11 RST WP Figure 1. 48-Lead TSOP (Normal Bend) Pinout LHF00L13 48-LEAD TSOP STANDARD PINOUT 12mm x 20mm TOP VIEW CCQ GND OE# 28 GND 27 CE Rev. 2.45 ...
Page 7
... CCQ pins. GND SUPPLY GROUND: Do not float any ground pins CONNECT: Lead is not internally connected; it may be driven or floated. LHF00L13 Table 1. Pin Descriptions Name and Function ) deselects the device and reduces power consumption RST# resets internal automation and inhibits write operations locked-down blocks cannot be unlocked ...
Page 8
... LHF00L13 [ 1EFFFF 64-Kword Block 39 1F0000 1EFFFF 64-Kword Block 38 1E0000 1DFFFF 64-Kword Block 37 1D0000 1CFFFF 64-Kword Block 36 1C0000 1BFFFF 64-Kword Block 35 1B0000 1AFFFF 64-Kword Block 34 1A0000 19FFFF 64-Kword Block 33 190000 18FFFF 64-Kword Block 32 180000 17FFFF 64-Kword Block 31 170000 16FFFF 64-Kword Block 30 160000 ...
Page 9
... Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down OTP OTP Lock OTP NOTES: 1. Block Address = The beginning location of a block address OTP-LK=OTP Block Lock configuration. 3. OTP=OTP Block data. LHF00L13 Address Code [ 000000H 000001H Block Address + 2 000080H ...
Page 10
... LHF00L13 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H Reserved for Future Implementation 000080H (DQ - Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used Rev. 2.45 ...
Page 11
... Command writes involving block erase, full chip erase, program or OTP program are reliably executed when V =V and V PP PPH1/2 5. Refer to Table 4 for valid D during a write operation Never hold OE# low and WE# low at the same timing. 7. Refer to Appendix of LHF00LXX series for more information about query code. LHF00L13 (1, 2) OE# WE# Address ...
Page 12
... If the program operation and the erase operation are both suspended, the suspended program operation will be resumed first. 8. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while the block erase operation is being suspended. LHF00L13 (10) Table 4. Command Definitions First Bus Cycle ...
Page 13
... Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP WP lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. IH 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LHF00L13 10 . When IL Rev. 2.45 ...
Page 14
... When the Set Block Lock-Down Bit command is written to the unlocked block (DQ corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written this state transitions table, assumes that WP# is not changed and fixed V LHF00L13 (5) and Block Lock-Down Erase/Program Allowed ...
Page 15
... State transition from the current state [011] to the next state depends on the previous state. 3. When WP# is driven automatically locked this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. LHF00L13 Result after WP# Transition (Next State) ( WP#=0→1 ...
Page 16
... LOW Detect, Operation Abort SR.2 = PROGRAM SUSPEND STATUS (PSS Program Suspended 0 = Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) LHF00L13 Table 8. Status Register Definition POPS VPPS PSS Status Register indicates the status of the WSM (Write State Machine) ...
Page 17
... A PP permanent connection to V =11.7V-12.3V is not allowed and can cause damage to the device. PP LHF00L13 *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the " ...
Page 18
... Figure 4. Transient Input/Output Reference Waveform for V V (min)/2 CCQ 1N914 R L =3.3KΩ DEVICE UNDER TEST Includes Jig Capacitances. Figure 5. Transient Equivalent Testing Load Circuit LHF00L13 Condition Min. V =0. =0.0V OUT /2 TEST POINTS CCQ (min) for a Logic "1" and 0.0V for a Logic "0". ...
Page 19
... Standby or Read Current PP I PPR I V Program Current PPW PP V Block Erase PPE Full Chip Erase Current V Program PP I PPWS Suspend Current I V Block Erase Suspend Current PPES PP LHF00L13 V =2.7V-3.6V CC Notes Min. Typ. Max. 1 -1.0 +1.0 1 -1.0 +1.0 1 Savings 1,4 1 1,7 17 ...
Page 20
... CC Applying 12.0V±0. during erase/program can only be done for a maximum of 1,000 cycles on each block may be connected to 12.0V±0.3V for a total of 80 hours maximum. 7. For all pins other than those shown in test conditions, input level is V LHF00L13 DC Characteristics (Continued) V =2.7V-3.6V CC Notes Min. ...
Page 21
... Output Hold from First Occurring Address, CE# or OE# change OH NOTES: 1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. Sampled, not 100% tested. ⎯ OE# may be delayed ELQV GLQV LHF00L13 (1) V =2.7V-3.6V, T =-40°C to +85° Parameter after the falling edge of CE# without impact to t ...
Page 22
... (A) 20 CE# ( OE# ( WE# ( High (D/Q) 15 (P) RST Figure 6. AC Waveform for Read Operations LHF00L13 VALID ADDRESS t AVAV t AVQV t ELQV t GLQV t GLQX t ELQX t PHQV 19 t EHQZ t GHQZ t OH VALID OUTPUT Rev. 2.45 ...
Page 23
... PP PP PPH1/2 (SR.1/3/4/5=0 after the Read Query or Read Identifier Codes/OTP command=t WHR0 EHR0 8. Refer to Table 4 for valid address and data for block erase, full chip erase, program, OTP program or lock bit configuration. LHF00L13 (1), (2) V =2.7V-3.6V, T =-40°C to +85° Parameter Notes =t =t ...
Page 24
... Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, OE# and CE# must be driven active, and WE# de-asserted. Figure 7. AC Waveform for Write Operations LHF00L13 NOTE 3 VALID ADDRESS t (t ...
Page 25
... If RST# asserted while a block erase, full chip erase, program or OTP program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding RST# low minimum 100ns is required after V also has been in stable there. LHF00L13 t PLPH (A) Reset during Read Array Mode SR.7=" ...
Page 26
... A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1" the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than t and its sequence is repeated, the block erase operation may not be finished. ERES LHF00L13 V =2.7V-3.6V, T =-40°C to +85°C CC ...
Page 27
... Related Document Information Document No. FUM03802 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. LHF00L13 (1) Document Name LHF00LXX series Appendix 24 Rev. 2.45 ...
Page 28
...
Page 29
...
Page 30
...
Page 31
...
Page 32
...
Page 33
...
Page 34
...
Page 35
...
Page 36
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
Page 37
A-1.1.1 Rise and Fall Time Symbol Parameter t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
Page 38
A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
Page 39
... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
Page 40
... ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 ...