W19B320ABT7H Winbond Electronics, W19B320ABT7H Datasheet
W19B320ABT7H
Specifications of W19B320ABT7H
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W19B320ABT7H Summary of contents
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... Output Disable Mode........................................................................................................9 6.1.9 Autoselect Mode...............................................................................................................9 6.1.10 Sector/Sector Block Protection and Unprotection...........................................................9 6.1.11 Write Protect (#WP) .....................................................................................................10 6.1.12 Temporary Sector Unprotect ........................................................................................10 6.1.13 Security Sector Flash Memory Region .........................................................................10 6.1.14 Hardware Data Protection ............................................................................................11 6.2 Command Definitions ................................................................................................... 12 6.2.1 Reading Array Data ........................................................................................................12 6.2.2 Reset Command.............................................................................................................12 6.2.3 AUTOSELECT Command Sequence ...
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DQ2: Toggle Bit II...........................................................................................................17 6.3.5 Reading Toggle Bits DQ6/DQ2 ......................................................................................17 6.3.6 DQ5: Exceeded Timing Limits ........................................................................................18 6.3.7 DQ3: Sector Erase Timer ...............................................................................................18 7. TABLE OF OPERATION MODES ............................................................................................ 19 7.1 Device Bus Operations ................................................................................................. 19 7.2 AUTOSELECT Codes (High ...
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Reset Waveform ........................................................................................................... 42 9.3 #BYTE Waveform for Read Operation ......................................................................... 43 9.4 #BYTE Waveform for Write Operation ......................................................................... 43 9.5 Programming Waveform............................................................................................... 44 9.6 Accelerated Programming Waveform........................................................................... 44 9.7 Chip/Sector Erase Waveform ....................................................................................... 45 9.8 Back-to back Read/Write ...
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... GENERAL DESCRIPTION The W19B320AT 32Mbit, 2.7~3.6-volt flexible bank CMOS flash memory organized × 16 bits. The word-wide (× 16) data appears on DQ15-DQ0, and byte-wide (x 8) data appears on DQ7-DQ0. The device can be programmed and erased in-system with a standard 3.0-volt power supply. A 12-volt V is not required. The unique cell architecture of the W19B320AT/B results in fast ...
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Write protect (#WP) function allows protection of two outermost boot sectors, regardless of sector protection status − Acceleration (ACC) function accelerates program timing 3. PIN CONFIGURATIONS (Top View, Balls Face Down) A6 A13 A5 A9 ...
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BLOCK DIAGRAM #CE #OE #WE #WP/ACC #BYTE #RESET DQ15/A A20 5. PIN DESCRIPTION SYMBOL A0 − A20 DQ0 − DQ14 DQ15/A-1 #CE #OE #WE #WP/ACC #BYTE #RESET RY/# ...
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... The internal state machine is set for reading array data when device power-up, or after hardware reset. This ensures that no excess modification of the memory content occurs during the power transition. In this mode there is no command necessary to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs ...
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... Simultaneous Read/Write Operations with Zero Latency This device is capable of simultaneously reading data from one bank of memory and programming/ erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). ...
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Hardware Reset Pin The #RESET pin provides a hardware method to reset the device to reading array data. When the #RESET pin is set to low for at least a period of t operation in progress, tri-states all ...
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... ID 6.1.13 Security Sector Flash Memory Region The Security Sector feature provides an OTP memory region that enables permanent device identification through an Electronic Serial Number (ESN). The Security Sector uses a Security Sector Indicator Bit (DQ7) to indicate whether the Security Sector is locked or not when shipped from the factory ...
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... Security Sector Protect Verify. The Security Sector protection must be used with caution, since there is no procedure available for unprotect the Security Sector area and none of the bits in the Security Sector memory space can be modified in any ways. 6.1.14 Hardware Data Protection The command sequence requirements of unlock cycles for programming or erasing provides data protection against negligent writes ...
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Command Definitions The device operation can be initiated by writing specific address and data commands or sequences into the command register. The device will be reset to reading array data when writing incorrect address and data values or writing ...
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... Exit Security Sector command sequence. The Exit Security Sector command sequence returns the device to normal operation. See “Security Sector Flash Memory Region” for further information. 6.2.4 Byte/Word Program Command Sequence The device can be programmed either by word or byte, which depending on the state of the #BYTE pin ...
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... Embedded Erase algorithm. The system preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or timings during these operations is not required in system. ...
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The time between these additional cycles must be less than 50 μ s; otherwise, erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. To ensure all commands are accepted, ...
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Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase ...
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During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either completed, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing ...
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DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not successfully completed. The ...
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TABLE OF OPERATION MODES 7.1 Device Bus Operations MODE #CE #OE Read L L Write Standby X ±0.3V Output Disable L H Reset X X Sector Protect L H Sector Unprotect L H Temporary X ...
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Sector Address Table (Top Boot Block) SECTOR ADDRESS BANK SECTOR A20-A12 SA0 000000XXX SA1 000001XXX SA2 000010XXX SA3 000011XXX SA4 000100XXX SA5 000101XXX SA6 000110XXX SA7 000111XXX SA8 001000XXX SA9 001001XXX SA10 001010XXX SA11 001011XXX SA12 001100XXX SA13 001101XXX ...
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Sector Address Table (Top Boot Block), continued. SECTOR ADDRESS BANK SECTOR A20-A12 SA41 101001XXX SA42 101010XXX SA43 101011XXX SA44 101100XXX SA45 101101XXX SA46 101110XXX SA47 101111XXX SA48 110000XXX SA49 110001XXX SA50 110010XXX SA51 110011XXX SA52 110100XXX SA53 110101XXX SA54 110110XXX ...
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Sector Address Table (Bottom Boot Block) SECTOR ADDRESS BANK SECTOR A20-A12 SA0 000000000 SA1 000000001 SA2 000000010 SA3 000000011 SA4 000000100 SA5 000000101 SA6 000000110 SA7 000000111 SA8 000001XXX SA9 000010XXX SA10 000011XXX SA11 000100XXX SA12 000101XXX SA13 000110XXX ...
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Sector Address Table (Bottom Boot Block), continued. SECTOR ADDRESS BANK SECTOR A20-A12 SA39 100000XXX SA40 100001XXX SA41 100010XXX SA42 100011XXX SA43 100100XXX SA44 100101XXX SA45 100110XXX SA46 100111XXX SA47 101000XXX SA48 101001XXX SA49 101010XXX SA50 101011XXX SA51 101100XXX SA52 101101XXX ...
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Top Boot Sector/Sector Block Address for Protection/Unprotection SECTOR A20-A12 SA0 000000XXX 000001XXX SA1-SA3 000010XXX 000011XXX SA4-SA7 0001XXXXX SA8-SA11 0010XXXXX SA12-SA15 0011XXXXX SA16-SA19 0100XXXXX SA20-SA23 0101XXXXX SA24-SA27 0110XXXXX SA28-SA31 0111XXXXX SA32-SA35 1000XXXXX SA36-SA39 1001XXXXX SA40-SA43 1010XXXXX SA44-SA47 1011XXXXX SA48-SA51 1100XXXXX SA52-SA55 ...
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Bottom Boot Sector/Sector Block Address for Protection/Unprotection SECTOR A20-A12 SA70 111111XXX 111110XXX SA69-SA67 111101XXX 111100XXX SA66-SA63 1110XXXXX SA62-SA59 1101XXXXX SA58-SA55 1100XXXXX SA54-SA51 1011XXXXX SA50-SA47 1010XXXXX SA46-SA43 1001XXXXX SA42-SA39 1000XXXXX SA38-SA35 0111XXXXX SA34-SA31 0110XXXXX SA30-SA27 0101XXXXX SA26-SA23 0100XXXXX SA22-SA19 0011XXXXX SA18-SA15 ...
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CFI Query Identification String DESCRIPTION Query-unique ASCII string "QRY" Primary OEM Command Set Address for primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternative OEM Extended table (00h = none exists) 7.5.1 System Interface ...
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Device Geometry Definition DESCRIPTION Device size =2 N bytes Flash device interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write=2 N (00h=not supported) Number of Erase Block Regions within devices Erase Block Region 1 ...
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Primary Vendor-Specific Extended Query DESCRIPTION Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Silicon Revision Number 01h = 0.18 μ m Erase suspend 0 = Not supported read only read ...
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... X = Don’t Care RA = Address of the memory location to be read Address of the memory location to be programmed. Addresses latch on the falling edge of the #WE or #CE pulse, whichever happens later Data to be programmed at location PA. Data latches on the rising edge of #WE or #CE pulse, whichever happens first. ...
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SA = Address of the sector to be verified (in AUTOSELECT mode) or erased. Address bits A20-A12 uniquely select any sector Address of the bank that is being switched to AUTOSELECT mode bypass mode ...
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Temporary Sector Unprotect Algorithm Notes: 1. All protected sectors unprotected (If #WP/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. START #RESET = V ID (Note 1) Perform Erase or ...
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In-System Sector Protect/Unprotect Algorithms START PLSCNT=1 #RESET=V ID Wait 1 μ Temporary Sector First Write Unprotect Mode Cycle=60h? Set up sector address Sector Protect: Write 60h to sector address with A6=0,A1=1,A0=0 Wait 150 μ s Verity Sector ...
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Security Sector Protect Verify Enter Security #RESET = V Write 60h to any address Write 40h to Security Sector Address with Read from Security Sector address with ...
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Erase Algorithm No Notes: See Command Definitions Table for erase command sequence details See DQ3 section for the sector erase timer details. 7.11 Data Polling Algorithm Notes Valid address for programming. During a sector ...
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Toggle Bit Algorithm Note: The system should recheck the toggle bit even if DQ5 =”1” because the toggle bit may stop toggling as DQ5 changes to “1”. See DQ6 and DQ2 section for more information START Read DQ7-DQ0 Read ...
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ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings PARAMETER Storage Temperature Plastic Packages Ambient Temperature with Power Applied V (Note 1) DD A9, #OE, and #RESET (Note 2) Voltage with Respect to Ground #WP/ACC All other pins (Note 1) Output Short ...
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DC Characteristics 8.3.1 CMOS Compatible PARAMETER SYM. Input Load Current A9 Input Load Current I Output Leakage Current I V Active Read Current DD I CC1 (Note Active Write Current DD I CC2 (Note 2, 3) ...
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AC Characteristics 8.4.1 Test Condition TEST CONDITION Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 8.4.2 AC Test Load and ...
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Read-Only Operations PARAMETER Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time From Address, #OE or ...
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Erase and Program Operation PARAMETER Write Cycle Timing (Note 1) Address setup Time #OE Address Setup Timing to low during toggle bit polling Address Hold Time #CE Address Hold Time From or toggle bit polling Data Setup Time Data ...
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Alternate #CE Controlled Erase and Program Operations PARAMETER Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover Time Before Write (#OE High to #WE Low) #WE Setup Time #WE ...
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TIMING WAVEFORMS 9.1 AC Read Waveform Address # #OE #WE Outputs #RESET RY/#BY 0V 9.2 Reset Waveform RY/#BY #OE,#CE #RESET Reset Timing NOT during Embedded Algorithms RY/#BY #OE,#CE #RESET T RC Addresses Stable T ACC ...
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Waveform for Read Operation #CE #OE #BYTE #BYTE Switching DQ0-DQ14 from word to byte mode DQ15/A-1 #BYTE #BYTE DQ0-DQ14 Switching from byte to word DQ15/A-1 mode 9.4 #BYTE Waveform for Write Operation #CE #WE #BYTE Note: Refer to ...
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Programming Waveform Program Command Sequence (last two cycles Address 555h #CE #OE # Data RY/#BY VDD T VCS Notes program address program data,D 2. Illustration shows device in ...
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Chip/Sector Erase Waveform Erase Command Sequence (last two cycl T WC Address 2AAh #CE # Data RY/#BY T VCS VDD Notes : sector address (for Sector Erase Valid Address for ...
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Polling Waveform (During Embedded Algorithms) Addresses T ACC T # #OE T OEH #WE DQ7 DQ0-DQ6 T BUSY RY/#BY Note: VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and ...
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DQ 2 vs. DQ6 Waveform Enter Erase Embedded Suspend Erasing #WE Erase DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The sysytem may use #OE or #CE to toggle DQ2 and DQ6. ...
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Alternate #CE Controlled Write (Erase/Program) Operation Timing 555 for program Address 2AA for erase #WE t GHEL #OE T #CE WS DATA T RH #RESET RY/#BY Notes: 1. Firgure indicates last two bus cycles of ...
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LATCHUP CHARACTERISTICS PARAMETER Input voltage with respect to V (including A9, #OE, and #RESET) Input voltage with respect Current DD Note : Includes all pins except V . Test conditions 11. CAPACITANCE PARAMETER SYM. ...
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ORDERING INFORMATION Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur ...
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PACKAGE DIMENSIONS 13.1 TFBGA48ball (6X8 mm^2, Ø=0.40mm) W19B320AT/B Publication Release Date: December 27, 2005 - 51 - Revision A4 ...
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Standard Thin Small Outline Package θ W19B320AT/B 48 MILLIMETER Sym. MIN. NOM. MAX 0.05 A2 0.95 1.00 E 18.3 18.4 18 19.8 20.0 20 11.9 ...
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VERSION HISTORY VERSION DATE A1 March 1, 2005 A2 April 14, 2005 A3 May 16, 2005 December 27, A4 2005 Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for ...