CY7C1381D-133BGXC Cypress Semiconductor Corp, CY7C1381D-133BGXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1381D-133BGXC
• Description: IC SRAM 18MBIT 133MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381D-133BGXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05544 Rev. *A
order. Leaving MODE unconnected will cause the device to
default to a interleaved burst sequence.
Interleaved Burst Address Table
(MODE = Floating or V
ZZ Mode Electrical Characteristics
Truth Table
Linear Burst Address Table (MODE = GND)
I
t
t
t
t
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
Address
Address
Parameter
after the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
A1: A0
A1: A0
Cycle Description
First
First
00
01
10
00
01
10
11
11
[ 3, 4, 5, 6, 7]
Address
Address
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Second
Second
A1: A0
A1: A0
01
00
10
01
10
00
11
11
DD
ADDRESS
External
External
External
)
Used
None
None
None
None
None
None
Address
Address
Description
A1: A0
A1: A0
Third
Third
10
11
00
01
10
11
00
01
CE
H
X
X
L
L
L
L
L
L
1
Address
Address
CE
Fourth
A1: A0
Fourth
A1: A0
X
X
X
X
H
H
H
L
L
PRELIMINARY
10
01
00
00
01
10
2
11
11
CE
H
X
X
X
X
X
L
L
L
3
ZZ
H
L
L
L
L
L
L
L
L
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
ADSP
Test Conditions
DD
DD
H
H
H
X
X
L
L
L
L
– 0.2V
– 0.2V
ADSC
L
X
X
L
L
X
X
X
L
ADV WRITE
1
X
X
X
X
X
X
X
X
X
X
, CE
. Writes may occur only on subsequent clocks
2
, CE
2t
Min.
X
X
X
X
X
X
X
X
L
CYC
0
3
[2]
, ADSP, and ADSC must
ZZREC
OE
X
X
X
X
X
X
H
X
L
CY7C1381D
CY7C1383D
2t
2t
Max.
80
CYC
CYC
after the ZZ input
CLK
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Q
L-H Tri-State
L-H D
X
Page 8 of 29
Tri-State
Unit
mA
DQ
ns
ns
ns
ns