CY7C1426AV18-167BZXC Cypress Semiconductor Corp, CY7C1426AV18-167BZXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1426AV18-167BZXC
• Description: IC SRAM 36MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1426AV18-167BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (4M x 9)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number: 38-05614 Rev. *C
Pin Definitions
D
WPS
NWS
NWS
BWS
BWS
A
Q
RPS
C
C
K
K
[x:0]
[x:0]
Pin Name
0
1
0
2
, BWS
, BWS
,
,
1
3
,
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Outputs-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Clock
Input-
Clock
Input-
Clock
I/O
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1411AV18 − D
CY7C1426AV18 − D
CY7C1413AV18 − D
CY7C1415AV18 − D
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D
Nibble Write Select 0, 1 − active LOW.(CY7C1411AV18 Only) Sampled on the rising edge of
the K and K clocks during Write operations. Used to select which nibble is written into the device
NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1426AV18 − BWS
CY7C1413AV18 − BWS
CY7C1415AV18 − BWS
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write opera-
tions. These address inputs are multiplexed for both Read and Write operations. Internally, the
device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1411AV18, 4M x 9 (4 arrays
each of 1M x 9) for CY7C1426AV18,2M x 18 (4 arrays each of 512K x 18) for CY7C1413AV18
and 1M x 36 (4 arrays each of 256K x 36) for CY7C1415AV18. Therefore, only 20 address inputs
are needed to access the entire memory array of CY7C1411AV18 and CY7C1426AV18, 19
address inputs for CY7C1413AV18 and 18 address inputs for CY7C1415AV18. These inputs are
ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K. when in single clock mode. When the Read port is deselected, Q
tri-stated.
CY7C1411AV18 − Q
CY7C1426AV18 − Q
CY7C1413AV18 − Q
CY7C1415AV18 − Q
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the C clock. Each Read access consists of a burst of
four sequential transfers.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q
0
controls D
[35:27].
[x:0]
to be ignored.
[3:0]
[7:0]
[8:0]
[17:0]
[35:0]
[7:0]
[8:0]
[17:0]
[35:0]
and NWS
0
0
0
controls D
controls D
controls D
1
controls D
[8:0]
[8:0]
[8:0]
[x:0]
[x:0]
, BWS
Pin Description
and BWS
when in single clock mode. All accesses are initiated
when in single clock mode.
[7:4]
1
.
controls D
1
controls D
[17:9]
, BWS
[17:9].
2
[x:0]
CY7C1426AV18
CY7C1413AV18
CY7C1415AV18
CY7C1411AV18
controls D
are automatically
[26:18]
Page 6 of 28
and BWS
3
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