CY14E064L-SZ35XI Cypress Semiconductor Corp, CY14E064L-SZ35XI Datasheet - Page 3

• Manufacturer Part Number: CY14E064L-SZ35XI
• Description: IC NVSRAM 64KBIT 35NS 28SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14E064L-SZ35XI

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (8.77mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Operation
The CY14E064L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14E064L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The CY14E064L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
the READ is initiated by an address transition, the outputs are
valid after a delay of t
by CE or OE, the outputs are valid at t
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs are stable prior to entering the
WRITE cycle and must remain stable until either CE or WE goes
HIGH at the end of the cycle. The data on the common IO pins
I/O
of a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers t
LOW.
Document Number: 001-06543 Rev. *E
0–7
are written into the memory if it is valid t
0–12
determines the 8,192 data bytes accessed. When
AA
(READ cycle 1). If the READ is initiated
AA
access time without the need for
ACE
or at t
HZWE
SD
, before the end
DOE
after WE goes
, whichever
AutoStore Operation
The CY14E064L stores data to nvSRAM using one of three
storage operations:
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E064L.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Figure 1
(V
Characteristics
the V
A pull up is placed on WE to hold it inactive during power up.
Figure 1. AutoStore Mode
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
CAP
CAP
) for automatic store operation. Refer to the
shows the proper connection of the storage capacitor
pin is driven to 5V by a charge pump internal to the chip.
1
14
on page 7 for the size of V
CC
pin drops below V
28
26
27
15
CAP
pin from V
CAP
CAP
CY14E064L
pin. This stored
SWITCH
. The voltage on
CC
CAP
DC Electrical
Page 3 of 17
. A STORE
, the part
capacitor.
CC
to
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