M25P05-AVDW6TP NUMONYX, M25P05-AVDW6TP Datasheet - Page 8

• Manufacturer Part Number: M25P05-AVDW6TP
• Description: IC FLASH 512KBIT 50MHZ 8TSSOP
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVDW6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M25P05-A
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25P05-A fea-
tures the following data protection mechanisms:
Table 2. Protected Area Sizes
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.
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BP1 Bit
– Power-up
Status Register
Power On Reset and an internal timer (t
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
0
0
1
1
Content
BP0 Bit
0
1
0
1
All sectors (Sectors 0 and 1)
No protection against Page Program (PP) and Sector Erase (SE)
All sectors (Sectors 0 and 1) protected against Bulk Erase (BE)
Protected Area
none
PUW
)
Memory Content
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
The Write Protect (W) signal, in co-operation
with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1,
BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the
Hardware Protected Mode (HPM).
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection, as all Write,
Program and Erase instructions are ignored.
completion
All sectors (Sectors 0 and 1)
Unprotected Area
none