CY7C1514V18-167BZI Cypress Semiconductor Corp, CY7C1514V18-167BZI Datasheet - Page 7

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CY7C1514V18-167BZI

Manufacturer Part Number
CY7C1514V18-167BZI
Description
IC SRAM 72MBIT 167MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1514V18-167BZI

Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
72M (2M x 36)
Speed
167MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1514V18-167BZI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock of the QDR II. In the
single clock mode, CQ is generated with respect to K
and CQ is generated with respect to K. The timing for
the echo clocks is shown in
21.
Application Example
Figure 2
Document #: 38-05489 Rev. *G
MASTER
ASIC)
(CPU
BUS
or
shows two QDR II used in an application.
CLKIN/CLKIN#
Delayed K#
DATA OUT
Source K#
Delayed K
Source K
DATA IN
Address
WPS#
BWS#
RPS#
Vt
R
R
Switching Characteristics
R = 50ohms
D
A
R
P
S
#
Vt = Vddq/2
W
P
S
#
SRAM #1
Figure 2. Application Example
W
B
S
#
C C#
on page
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
DLL
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the DLL is locked after 1024
cycles of stable clock. The DLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock to the
desired frequency. The DLL automatically locks 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note
QDRII/DDRII/QDRII+/DDRII+.
D
A
R
Vt
Vt
R
P
#
S
W
P
S
#
AN5062, DLL Considerations in
W
B
S
#
SRAM #2
C C#
CY7C1512V18
CY7C1514V18
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
Page 7 of 26
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