CY7C1565V18-400BZC Cypress Semiconductor Corp, CY7C1565V18-400BZC Datasheet - Page 23

• Manufacturer Part Number: CY7C1565V18-400BZC
• Description: IC SRAM 72MBIT 400MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1565V18-400BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-05384 Rev. *F
Parameter
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
24. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
25. This part has a voltage regulator internally; t
26. These parameters are extrapolated from the input timing parameters (t
27. t
28. At any given voltage and temperature t
29. t
30. Hold to >V
POWER
CYC
KH
KL
KHKH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
QVLD
KC Var
KC lock
KC Reset
operated and outputs data with the output timings of that frequency range.
in the t
voltage.
CHZ
QVLD
CY
, t
CLZ
spec is applicable for both rising and falling edges of QVLD signal.
KHKH
, are specified with a load capacitance of 5 pF as in part (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IH
Consortium
KHKH
KHKL
KLKH
KHKH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
CQHQVLD
KC Var
KC lock
KC Reset
). These parameters are only guaranteed by design and are not tested in production.
Parameter
or <V
IL
.
V
K Clock Cycle Time
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
K Clock Rise to K Clock Rise
(rising edge to rising edge)
Address Setup to K Clock Rise
Control Setup to K Clock Rise (RPS, WPS)
Double Data Rate Control Setup to Clock (K/K)
Rise (BWS
D
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS)
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS
D
K/K Clock Rise to Data Valid
Data Output Hold after Output K/K Clock Rise
(Active to Active)
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
Clock (K/K) Rise to High-Z
(Active to High-Z)
Clock (K/K) Rise to Low-Z
Echo Clock High to QVLD Valid
Clock Phase Jitter
DLL Lock Time (K)
K Static to DLL Reset
DD
[X:0]
[X:0]
[23, 24]
(Typical) to the First Access
Hold after Clock (K/K) Rise
Setup to Clock (K/K) Rise
CHZ
0
0
is less than t
POWER
, BWS
, BWS
is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated.
Description
[26, 27]
1
1
, BWS
, BWS
CLZ
[30]
and t
2
2
[26, 27]
, BWS
, BWS
CHZ
[26]
KHKH
“AC Test Loads and Waveforms”
less than t
[29]
[25]
3
3
[26]
)
)
- 250ps, where 250ps is the internal jitter. An input jitter of 200ps(t
CO
.
–0.45
–0.45
–0.45
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20
2048
2.50 8.40 2.66 8.40
1.06
0.28
0.28
0.28
0.28
–0.2
0.81
0.81
Min Max Min Max Min Max Min Max
0.4
0.4
0.4
0.4
0.4
0.4
400 MHz
30
1
–
0.45
0.45
0.45
0.20
CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
0.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
on page 22. Transition is measured ± 100 mV from steady-state
–0.45
–0.45
–0.45
2048
–0.2
1.13
0.28
0.28
0.28
0.28
0.88
0.88
0.4
0.4
0.4
0.4
0.4
0.4
375 MHz
30
1
–
–
–
–
0.45
0.45
0.45
0.20
0.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–0.45
–0.45
–0.45
2048
1.28
0.28
0.28
0.28
0.28
–0.2
1.03
1.03
3.0
0.4
0.4
0.4
0.4
0.4
0.4
333 MHz
30
1
–
–
–
–
8.40
0.45
0.45
0.45
0.20
0.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
KCVAR
–0.45
–0.45
–0.45
2048
1.40
0.28
0.28
0.28
0.28
–0.2
1.15
1.15
3.3
0.4
0.4
0.4
0.4
0.4
0.4
300 MHz
30
–
1
–
–
–
) is already included
Page 23 of 28
8.40
0.45
0.45
0.45
0.20
0.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
cycles
t
t
Unit
CYC
CYC
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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