M29W640FB70N6F NUMONYX, M29W640FB70N6F Datasheet - Page 16

• Manufacturer Part Number: M29W640FB70N6F
• Description: IC FLASH 64MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W640FB70N6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M29W640FB70N6FTR

3.5
3.6
3.6.1
3.6.2
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Automatic Standby
If CMOS levels (V
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, I
Read operation is in progress.
Special Bus operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require V
applied to some pins.
Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in
Bus operations, BYTE = V
Block Protect and Chip Unprotect
Groups of blocks can be protected against accidental Program or Erase. The Protection
Groups are shown in
can be unprotected to allow the data inside the blocks to be changed.
The V
V
protected regardless of the Block Protection Status or the Reset/Block Temporary
Unprotect pin status.
Block Protect and Chip Unprotect operations are described in
PP
/Write Protect is at V
PP
/Write Protect pin can be used to protect the two outermost boot blocks. When
CC
± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
Appendix A: Block addresses Table 21
IL
IL
the two outermost boot blocks are protected and remain
and
CC2
Table 5: Bus operations, BYTE = V
. The Data Inputs/Outputs will still output data if a Bus
and
Appendix D: Block
Table
IH
.
22. The whole chip
ID
protection.
Table 4:
to be