M29W640GB70ZA6F NUMONYX, M29W640GB70ZA6F Datasheet - Page 29
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M29W640GB70ZA6F
Manufacturer Part Number
M29W640GB70ZA6F
Description
IC FLASH 64MBIT 70NS 48TFBGA
Manufacturer
NUMONYX
Series
Axcell™r
Datasheet
1.M29W640GH70NB6E.pdf
(90 pages)
Specifications of M29W640GB70ZA6F
Format - Memory
FLASH
Memory Type
FLASH - Nor
Memory Size
64M (8Mx8, 4Mx16)
Speed
70ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TFBGA
Cell Type
NOR
Density
64Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TFBGA
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4M
Supply Current
10mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M29W640GB70ZA6FCT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M29W640GB70ZA6F
Manufacturer:
MICRON
Quantity:
101
Company:
Part Number:
M29W640GB70ZA6F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
4.2.3
4.2.4
Note:
Octuple Byte Program command
This is used to write eight adjacent bytes, in x8 mode, simultaneously. The addresses of the
eight bytes must differ only in A1, A0 and DQ15A-1.
12 V must be applied to the V
Program command. Care must be taken because applying a 12 V voltage to the V
will temporarily unprotect any protected block.
Nine bus write cycles are necessary to issue the command:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Double Word Program command
The Double Word Program command is used to write a page of two adjacent words in
parallel. The two words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double Word Program command:
After the program operation has completed the memory will return to the read mode, unless
an error has occurred. When an error occurs bus read operations will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
Note that the fast program commands cannot change a bit set to ’0’ back to ’1’. One of the
erase commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical program times are given in
It is not necessary to raise V
The first bus cycle sets up the command.
The second bus cycle latches the address and the data of the first byte to be written
The third bus cycle latches the address and the data of the second byte to be written
The fourth bus cycle latches the address and the data of the third byte to be written
The fifth bus cycle latches the address and the data of the fourth byte to be written
The sixth bus cycle latches the address and the data of the fifth byte to be written
The seventh bus cycle latches the address and the data of the sixth byte to be written
The eighth bus cycle latches the address and the data of the seventh byte to be written
The ninth bus cycle latches the address and the data of the eighth byte to be written
and starts the program/erase controller.
The first bus cycle sets up the Double Word Program command
The second bus cycle latches the address and the data of the first word to be written
The third bus cycle latches the address and the data of the second word to be written
and starts the program/erase controller.
PP
PP
/WP to 12 V before issuing this command.
/Write Protect pin, V
Table 12: Program, erase times and endurance
PP
/WP, prior to issuing an Octuple Byte
PP
cycles.
/WP pin
29/90