CY7C1250V18-333BZXC Cypress Semiconductor Corp, CY7C1250V18-333BZXC Datasheet

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... K and K. Read data is driven on the rising edges of both K and K. Each address location is associated with two 8-bit words (CY7C1246V18), 9-bit words (CY7C1257V18), 18-bit words (CY7C1248V18), or 36-bit words (CY7C1250V18) that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ) ...

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... Logic Block Diagram (CY7C1257V18 (20:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [0] Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Write Write Reg Reg Output Logic Control Read Data Reg Reg. Reg. 8 Reg. Write Write Reg Reg Output Logic Control Read Data Reg ...

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... Logic Block Diagram (CY7C1248V18 (19:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1250V18 (18:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 ...

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... NC NC DQ5 DOFF REF DDQ DQ6 DQ7 R TDO TCK NC/72M DQ4 DQ5 DOFF REF DDQ DQ6 DQ7 R TDO TCK A Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 CY7C1246V18 ( NC/144M R/W NWS NC/288M K NWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ QVLD ...

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... DQ26 R TDO TCK A Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 CY7C1248V18 ( NC/144M R/W BWS NC/288M K BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ QVLD CY7C1250V18 ( R/W BWS K BWS BWS BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ QVLD ...

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... These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each for CY7C1246V18 arrays each for CY7C1257V18 arrays each 18) for CY7C1248V18, and arrays each of 512K x 36) for CY7C1250V18. R/W Input- Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address ...

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... Power Supply Power Supply Inputs to the Core of the Device Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Description output impedance are set to 0.2 x RQ, where [x:0] Page [+] Feedback [+] Feedback ...

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... Functional Overview The CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input and output timing refer to the rising edge of the input clocks (K and K). ...

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... Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 Truth Table The truth table for the CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 follows. Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: (2.0 cycle Latency) Load address ...

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... Assumes a write cycle was initiated per the Write Cycle Descriptions of a write cycle, as long as the setup and hold requirements are met. Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 [2, 8] Comments ) are written into the device. [7:0] ) are written into the device. ...

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... Write Cycle Descriptions The write cycle descriptions table for CY7C1250V18 follows. BWS BWS BWS BWS L – L – L – L – L – L – Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 [ Comments – During the data portion of a write sequence, all four bytes (D into the device ...

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... TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in page 15 ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 [9] 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- ...

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... These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in 11. Overshoot: V (AC) < 0.3V (pulse width less than t IH DDQ 12. All voltage refers to ground. Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 0 Bypass Register Instruction Register ...

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... CH 14. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-06348 Rev. *D Description [14] Figure 2. TAP Timing and Test Conditions 50Ω 1. TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Min Max Unit MHz ALL INPUT PULSES 0.9V t TCYC ...

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... RESERVED 011 SAMPLE/PRELOAD 100 RESERVED 101 RESERVED 110 BYPASS 111 Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Value CY7C1257V18 CY7C1248V18 000 000 00000110100 00000110100 1 1 Description Captures the input/output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO ...

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... Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...

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... Clock Start (Clock Starts after DDQ is Stable DDQ DDQ Stable (< + 0.1V DC per 50 ns) DOFF Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ ...

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... Inputs Static Test Conditions (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175Ω < RQ < 350Ω. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Ambient [15] [15 DDQ 1.8 ± 0.1V 1. Min Typ Max Unit 1 ...

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... R = 50Ω REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Max Unit 165 FBGA Unit Package °C/W 16.25 °C/W 2.91 [20] ALL INPUT PULSES 1.25V 0.75V Slew Rate = 2 V/ns = 0.75V 250Ω ...

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... CLZ voltage. 25. At any voltage and temperature t is less than t CHZ 26. t spec is applicable for both rising and falling edges of QVLD signal. QVLD 27. Hold to >V or < Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Description [22] , BWS ) BWS ) 2 3 –0.45 [23] [23] [24, 25] [24, 25] – ...

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... NOP NOP NOP WRITE QVLD Q00 Q01 Q10 Q11 D20 D21 t t DOH CHZ CQD t CQDOH t CCQO t CCQO CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 WRITE READ NOP NOP QVLD Q40 Q41 D30 D31 t t CQH CQHCQH DON’T CARE UNDEFINED Page [+] Feedback [+] Feedback ...

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... Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1257V18-333BZC CY7C1248V18-333BZC CY7C1250V18-333BZC CY7C1246V18-333BZXC 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1257V18-333BZXC CY7C1248V18-333BZXC CY7C1250V18-333BZXC CY7C1246V18-333BZI 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1257V18-333BZI CY7C1248V18-333BZI CY7C1250V18-333BZI CY7C1246V18-333BZXI 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free ...

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... Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1257V18-300BZI CY7C1248V18-300BZI CY7C1250V18-300BZI CY7C1246V18-300BZXI 51-85195 165-ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1257V18-300BZXI CY7C1248V18-300BZXI CY7C1250V18-300BZXI Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Package Type Commercial Operating Range Industrial Page [+] Feedback [+] Feedback ...

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... Package Diagram Figure 6. 165-ball FBGA ( 1.40 mm), 51-85195 Document Number: 001-06348 Rev. *D CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 51-85195-*A Page [+] Feedback [+] Feedback ...

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... Document History Page Document Title: CY7C1246V18/CY7C1257V18/CY7C1248V18/CY7C1250V18, 36-Mbit DDR-II+ SRAM 2-Word Burst Ar- chitecture (2.0 Cycle Read Latency) Document Number: 001-06348 REV. ECN No. Issue Date ** 425689 See ECN *A 461639 See ECN *B 497628 See ECN *C 1093183 See ECN *D 2198506 See ECN VKN/AESA Added footnote# 19 related to I © ...