CY14E256L-SZ25XCT Cypress Semiconductor Corp, CY14E256L-SZ25XCT Datasheet - Page 3

• Manufacturer Part Number: CY14E256L-SZ25XCT
• Description: IC NVSRAM 256KBIT 25NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14E256L-SZ25XCT

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Configurations
Table 1. Pin Definitions
Document Number: 001-06968 Rev. *H
Pin Name
DQ
A
V
HSB
0
V
V
WE
CE
OE
0
–A
CAP
SS
CC
-DQ
14
7
Alt
W
G
E
Input or Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
Power Supply Power Supply Inputs to the Device.
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
I/O Type
Ground
Input
Input
Input
Input
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
to nonvolatile elements.
Figure 1. Pin Diagram: 32-Pin SOIC/DIP
Description
CY14E256L
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