CY14E256L-SZ25XCT Cypress Semiconductor Corp, CY14E256L-SZ25XCT Datasheet - Page 4

• Manufacturer Part Number: CY14E256L-SZ25XCT
• Description: IC NVSRAM 256KBIT 25NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14E256L-SZ25XCT

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Operation
The CY14E256L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables storage and recall
of all cells in parallel. During the STORE and RECALL opera-
tions, SRAM READ and WRITE operations are inhibited. The
CY14E256L supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The CY14E256L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
the READ is initiated by an address transition, the outputs are
valid after a delay of t
by CE or OE, the outputs are valid at t
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ
the end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common I/O lines. If OE is left
LOW, internal circuitry turns off the output buffers t
goes LOW.
AutoStore Operation
The CY14E256L stores data to nvSRAM using one of three
storage operations:
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E256L.
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Figure 2
(V
Document Number: 001-06968 Rev. *H
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
CAP
) for automatic store operation. A charge storage capacitor
0–7
0–14
shows the proper connection of the storage capacitor
are written into the memory if it has valid t
determines the 32,768 data bytes accessed. When
AA
CC
(READ cycle 1). If the READ is initiated
pin drops below V
AA
access time without the need for
CAP
pin from V
ACE
CAP
or at t
SWITCH
pin. This stored
DOE
CC
HZWE
CAP
. A STORE
, whichever
SD
, the part
capacitor.
after WE
, before
CC
to
having a capacitor of between 68 uF and 220 uF (+ 20%) rated
at 6V should be provided. The voltage on the V
to 5V by a charge pump internal to the chip. A pull up is placed
on WE to hold it inactive during power up.
Figure 2. AutoStore Mode
In system power mode, both V
+5V power supply without the 68 μF capacitor. In this mode, the
AutoStore function of the CY14E256L operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
STORE cycle.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull up resistor is shown connected to
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc
reaches V
between V
of current between V
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then V
is tied to ground and + 5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the CY14E256L is operated in this configuration,
references to V
sheet. In this mode, STORE operations are triggered through
software control or the HSB pin. To enable or disable Autostore
using an I/O port pin see
permissible to change between these three options ”on the fly”.
SWITCH
CC
and the system supply to avoid momentary excess
CC
CC
, then a 2.2 ohm resistor should be connected
are changed to V
does not drop below 3.6V during the 10 ms
CC
and V
“Preventing Store”
CC
CAP
and V
.
CAP
CAP
CAP
throughout this data
are connected to the
CY14E256L
on page
(Figure
CAP
Page 4 of 19
pin is driven
3). This is
6.
It is not
HSB.
CC
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