MD2533-D8G-X-P/Y SanDisk, MD2533-D8G-X-P/Y Datasheet - Page 45

• Manufacturer Part Number: MD2533-D8G-X-P/Y
• Description: IC MDOC H3 8GB FBGA
• Manufacturer: SanDisk
• Type: Flash Disk Moduler

Specifications of MD2533-D8G-X-P/Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V, 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 115-LFBGA
• Density: 1GByte
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: FBGA
• Mounting: Surface Mount
• Pin Count: 115
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.65/2.7V
• Operating Supply Voltage (max): 1.95/3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / Rohs Status: Compliant

Note: 1. This register cannot be accessed when the A0 signal is pulled high. Therefore it is
7.3.9 Burst Write Mode Exit Register
Description:
Address (hex): 9404 (128KB window) / 1404 (8KB window)
Type:
Read/Write
Bit Name
Reset Value
45
HOLD
LENGTH
LATENCY
WAIT_STATE
BURST_EN
2. Burst mode can only be used in conjunction with mDOC H3 DMA functionality.
recommended that A0 will be connected to Host CPU A0, or to VSS.
D15-D0
W
RFU
N/A
Write to this 16-bit register takes the device out of Burst Write mode
Write
Specifies if the data output/input on D [15:0] during burst mode read/write
cycles should be held for one or two clock cycle.
0: Data is held for one clock cycle.
1: Data is held for two clock cycles.
Specifies the number of words to be transferred in each burst cycle, as follows:
0: 4 Words
1: 8 Words
2: 16 Words
3: 32 Words
Controls the number of clock cycles between assertion of CE# and availability
of the first word of data to be latched by the host. The number of clock cycles is
equal to 2 + LATENCY.
If HOLD = 1, then the data is available to be latched on this clock and on the
subsequent clock.
The number of clocks from the [N-1] access until the assertion of CE#.
0: When host reads word N there is no CLK.
1: When host reads word N there is CLK
2-3: After the host reads word N there are 1 or 2 additional clocks until CE#
deassertion.
Note: In Burst write the wait states start from the N word.
Enables burst mode cycles.
0: Burst mode is disabled.
1: Burst mode is enabled.
Data Sheet (Preliminary) Rev. 0.2
mDOC H3 Embedded Flash Drive
92-DS-1205-10