CAT93C66XI ON Semiconductor, CAT93C66XI Datasheet - Page 7

• Manufacturer Part Number: CAT93C66XI
• Description: IC EEPROM 4KBIT 2MHZ 8SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT93C66XI

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 4Kb
• Interface Type: Serial (Microwire)
• Organization: 512x8/256x16
• Frequency (max): 500KHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC EIAJ
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be
deselected for a minimum of t
CS will start the self clocking clear and data store cycle
of the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C66 can be determined by
selecting the device and polling the DO pin. Since this
device features Auto-Clear before write, it is NOT
necessary to erase a memory location before it is
written into.
Figure 3. EWEN/EWDS Instruction Timing
Figure 4. Write Instruction Timing
Figure 5. Erase Instruction Timing
© 2009 SCILLC. All rights reserved
Characteristics subject to change without notice
SK
CS
DO
SK
CS
DI
DI
DO
CS
SK
DI
1
1
1
0
0
1
0
CSMIN
1
* ENABLE = 11
1
DISABLE = 00
A N
. The falling edge of
*
A N
A N-1
A N-1
HIGH-Z
HIGH-Z
A 0
D N
7
A 0
Erase
Upon receiving an ERASE command and address,
the CS (Chip Select) pin must be deasserted for a
minimum of t
will start the self clocking clear cycle of the selected
memory location. The clocking of the SK pin is not
necessary after the device has entered the self
clocking mode. The ready/ busy status of the
CAT93C66 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
D 0
t SV
t SV
CSMIN
t EW
t EW
t CSMIN
STATUS VERIFY
STANDBY
STATUS
VERIFY
t CS
BUSY
BUSY
(Figure 5). The falling edge of CS
READY
READY
HIGH-Z
STANDBY
STANDBY
t HZ
t HZ
HIGH-Z
Doc. No. MD-1089 Rev. T
CAT93C66