EPC4QI100 Altera, EPC4QI100 Datasheet - Page 79
![IC CONFIG DEVICE 4MBIT 100-PQFP](/photos/6/70/67066/544-100-pqfp_sml.jpg)
EPC4QI100
Manufacturer Part Number
EPC4QI100
Description
IC CONFIG DEVICE 4MBIT 100-PQFP
Manufacturer
Altera
Series
EPCr
Datasheet
1.EPC4QI100N.pdf
(116 pages)
Specifications of EPC4QI100
Programmable Type
In System Programmable
Memory Size
4Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-MQFP, 100-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2189
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPC4QI100
Manufacturer:
ALTERA
Quantity:
1
Part Number:
EPC4QI100
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPC4QI100N
Manufacturer:
ALTERA
Quantity:
300
Part Number:
EPC4QI100N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Timing Information
Timing Information
Figure 3–18. Write Operation Timing
Table 3–16. Write Operation Parameters
© December 2009
f
t
t
t
t
t
t
t
t
t
t
t
Note to
(1) These parameters are not shown in
WCLK
CH
CL
NCSSU
NCSH
DSU
DH
CSH
WB
WS
EB
ES
(1)
(1)
(1)
(1)
Symbol
Table
3–16:
Altera Corporation
Write clock frequency (from FPGA, download cable, or
embedded processor) for write enable, write disable,
read status, read silicon ID, write bytes, erase bulk, and
erase sector operations
DCLK high time
DCLK low time
Chip select (nCS) setup time
Chip select (nCS) hold time
Data (ASDI) in setup time before rising edge on DCLK
Data (ASDI) hold time after rising edge on DCLK
Chip select high time
Write bytes cycle time for EPCS1, EPCS4, EPCS16, and
EPCS64
Write bytes cycle time for EPCS128
Write status cycle time
Erase bulk cycle time for EPCS1
Erase bulk cycle time for EPCS4
Erase bulk cycle time for EPCS16
Erase bulk cycle time for EPCS64
Erase bulk cycle time for EPCS128
Erase sector cycle time for EPCS1, EPCS4, EPCS16,
and EPCS64
Erase sector cycle time for EPCS128
Figure 3–18
device.
Table 3–16
operation.
DCLK
DATA
ASDI
nCS
t
NCSH
Figure
High Impedance
defines the serial configuration device timing parameters for write
t
DSU
shows the timing waveform for write operation to the serial configuration
Parameter
3–18.
Bit n
t
NCSSU
t
DH
Bit n 1
t
CH
t
CL
Bit 0
Min
100
Configuration Handbook (Complete Two-Volume Set)
10
—
—
20
20
10
—
—
—
—
—
—
—
—
—
5
5
t
CSH
105
Typ
1.5
2.5
—
—
—
—
—
—
—
—
17
68
5
3
5
2
2
Max
160
250
25
—
—
—
—
—
—
—
15
10
40
5
7
6
3
6
MHz
Unit
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
3–27