AT17C002-10JI Atmel, AT17C002-10JI Datasheet
AT17C002-10JI
Specifications of AT17C002-10JI
Related parts for AT17C002-10JI
AT17C002-10JI Summary of contents
Page 1
... Replacement for AT17C/LV020 Description The AT17C002 and AT17LV002 (high-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration mem- ory for programming Field Programmable Gate Arrays. The AT17 Series is packaged in the popular 8-lead LAP, 20-lead PLCC, 44-lead PLCC and the 44-lead TQFP. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices ...
Page 2
Pin Configuration 8-lead LAP DATA 1 CLK 2 RESET/ 44-lead PLCC WP1 AT17C/LV002 2 8 VCC ...
Page 3
Block Diagram SER_EN WP1 OSC CONTROL OSC POWER ON RESET CLK READY Device Description 2281D–12/01 PROGRAMMING MODE LOGIC ROW ADDRESS COUNTER BIT COUNTER RESET/OE CE The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter- face directly with ...
Page 4
Pin Configurations LAP PLCC TQFP PLCC Pin Pin Pin Pin – ...
Page 5
FPGA Master Serial Mode Summary Control of Configuration Cascading Serial Configuration EEPROMs AT17 Series Reset Polarity Programming Mode Standby Mode 2281D–12/01 The I/O and logic functions of any SRAM-based FPGA are established by a configura- tion program. The program is ...
Page 6
Example Circuits Figure 1. AT17 Series Device for Programming PSLI Devices AT40K/AT40KAL/AT94K RESET RESET GND Notes: 1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the ...
Page 7
... For details of ISP, please refer to the “Programming Specification for Atmel's AT17 and AT17A Series FPGA Configuration EEPROMs”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf. Figure 3. In-System Programming of AT17 Series for PSLI Applications AT40K/AT40KAL/AT94K RESET RESET GND Notes: 1. Reset polarity must be set to active Low. ...
Page 8
... This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- +0.5V ating conditions is not implied. Exposure to Abso- CC lute Maximum Rating conditions for extended periods of time may affect device reliability. AT17C002 AT17LV002 Min Max Min Max Units 4.75 5 ...
Page 9
DC Characteristics ± 5% Commercial, 5V ± 10% Industrial/Military CC Symbol Description V High-Level Input Voltage IH V Low-level input voltage IL V High-level Output Voltage ( Low-level Output Voltage ( High-level Output ...
Page 10
AC Characteristics CE RESET/OE CLK T CE DATA AC Characteristics when Cascading RESET/OE CE CLK T CDF LAST BIT DATA T OCK CEO AT17C/LV002 10 T SCE CAC T OCE T SCE T ...
Page 11
... Maximum Input Clock Frequency MAX Notes: 1. Preliminary specifications for military operating range only test load = 50 pF. 3. Float delays are measured with loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for AT17C002 when Cascading ± 5% Commercial ± 10% Industrial/Military CC CC ...
Page 12
AC Characteristics for AT17LV002 V = 3.3V ± 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (2) T CLK to Data Delay CAC T Data Hold From CE ...
Page 13
... Plastic Leaded Chip Carrier (PLCC) Thin Plastic Quad Flat Package (TQFP) Plastic Leaded Chip Carrier (PLCC) Note: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0636.pdf. 2281D–12/01 (1) θ [°C/W] JC 8CN4 ...
Page 14
... Plastic J-leaded Chip Carrier (PLCC) 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT17C/LV002 14 Ordering Code AT17C002-10CC AT17C002-10JC AT17C002-10TQC AT17C002-10BJC AT17C002-10CI AT17C002-10JI AT17C002-10TQI AT17C002-10BJI Ordering Code AT17LV002-10CC AT17LV002-10JC AT17LV002-10BJC AT17LV002-10CI AT17LV002-10JI AT17LV002-10TQI AT17LV002-10BJI Package Type Package ...
Page 15
Packaging Information 8CN4 – LAP Marked Pin1 Indentifier E 0.10 mm TYP Bottom View Note: 1. Metal Pad Dimensions. 1150 E.Cheyenne Mtn Blvd. Colorado Springs, CO 80906 R 2281D–12/01 D Top View Side View ...
Page 16
PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension ...
Page 17
TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...
Page 18
PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
Page 19
... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...