AT17C512-10CC Atmel, AT17C512-10CC Datasheet
AT17C512-10CC
Specifications of AT17C512-10CC
Related parts for AT17C512-10CC
AT17C512-10CC Summary of contents
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... Low-power Standby Mode Description The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con- figuration memory for programming Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-lead LAP, 8-lead PDIP and the popular 20-lead PLCC. The AT17 Series uses a simple serial-access procedure to configure one or more FPGA devices ...
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... Pin Configurations AT17C512/010/LV512/010 2 8-lead LAP DATA 1 8 VCC CLK 2 7 SER_EN RESET/ CEO (A2 GND 8-lead PDIP DATA 1 8 VCC CLK 2 7 SER_EN RESET/ CEO (A2 GND 20-lead PLCC CLK 4 18 WP1 5 17 RESET/ WP2 SER_EN NC READY CEO (A2) 0944E–12/01 ...
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... DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. AT17C512/010/LV512/010 PROGRAMMING DATA SHIFT REGISTER ...
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... READY 7 17 SER_EN Note: 1. This pin is not available on the 8-lead packages. AT17C512/010/LV512/010 4 I/O Description I/O Three-state DATA output for configuration. Open-collector bi-directional pin for programming. I Clock input. Used to increment the internal address and bit counter for reading and programming. I WRITE PROTECT (1). Used to protect portions of memory during programming. ...
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... The AT17LV parts are read/write at 3.3V nominal. The AT17C/LV512/010 Series Configurator enters a low-power standby mode when- ever CE is asserted High. In this mode, the Configurator consumes less than 0 current at 5V. The output remains in a high-impedance state regardless of the state of the OE input. AT17C512/010/LV512/010 (except during ISP). CC supply only. CC ...
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... Figure 2. Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications PROGRAM PROGRAM GND Notes: 1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices internal pull-up resistor is enabled here for DONE. AT17C512/010/LV512/010 6 DATA0 CCLK CON INIT 4.7 k XILINX FPGA ...
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... Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices internal pull-up resistor is enabled here for DONE. 0944E–12/01 DATA0 DATA CCLK CLK CON CE INIT RESET/ 4.7 k XILINX FPGA DIN CCLK (3) DONE INIT AT17C512/010/LV512/010 4.7 k 4.7 k DATA SCLK GND AT17 Series Device SER_EN (1) (2) READY ...
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... V CC -40°C to +85°C Military Supply voltage relative to GND -55°C to +125°C AT17C512/010/LV512/010 8 *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- +0 ...
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... High-level Output Voltage ( Low-level Output Voltage ( High-level Output Voltage ( Low-level Output Voltage ( Supply Current, Active Mode CCA I Input or Output Leakage Current ( Supply Current, Standby Mode CCS 0944E–12/01 AT17C512/010/LV512/010 = -4 mA) OH Commercial = +4 mA mA) OH Industrial = +4 mA mA) OH Military = +4 mA GND Commercial Industrial/Military = -2 ...
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... AC Characteristics CE RESET/OE CLK T CE DATA AC Characteristics when Cascading RESET/OE CE CLK T CDF LAST BIT DATA T OCK CEO AT17C512/010/LV512/010 10 T SCE CAC T OCE T SCE T HOE FIRST BIT T OOE T OCE T HCE 0944E–12/01 ...
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... MAX Input Clock Frequency MAX Notes: 1. Preliminary specifications for military operating range only test load = 50 pF. 3. Float delays are measured with loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for AT17C512/010 when Cascading V = 5V± 5% Commercial ± 10% Industrial/Military CC CC ...
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... RESET/OE to CEO Delay OOE F MAX Input Clock Frequency MAX Notes: 1. Preliminary specifications for military operating range only test load = 50 pF. 3. Float delays are measured with loads. Transition is measured ± 200 mV from steady state active levels. AT17C512/010/LV512/010 12 Commercial Industrial/Military Min Max Min 50 55 ...
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... Leadless Array Package (LAP) Plastic Dual Inline Package (PDIP) Plastic Leaded Chip Carrier (PLCC) Note: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0636.pdf. 0944E–12/01 AT17C512/010/LV512/010 (1) θ [°C/W] JC 8CN4 45 8P3 37 20J 35 θ ...
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... Ordering Information – 5V Devices Memory Size Ordering Code 512-Kbit AT17C512-10CC AT17C512-10PC AT17C512-10JC AT17C512-10CI AT17C512-10PI AT17C512-10JI 1-Mbit AT17C010-10CC AT17C010-10PC AT17C010-10JC AT17C010-10CI AT17C010-10PI AT17C010-10JI Ordering Information – 3.3V Devices Memory Size Ordering Code 512-Kbit AT17LV512-10CC AT17LV512-10PC AT17LV512-10JC AT17LV512-10CI AT17LV512-10PI AT17LV512-10JI 1-Mbit AT17LV010-10CC AT17LV010-10PC ...
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... E.Cheyenne Mtn Blvd. Colorado Springs, CO 80906 R 0944E–12/01 D Top View Side View Pin1 Corner TITLE 8CN4, 8-lead ( 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) AT17C512/010/LV512/010 A A1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b ...
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... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001 BA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT17C512/010/LV512/010 16 D PIN PLACES TITLE 8P3, 8-lead (0.300"/7.62 mm Wide) Plastic Dual ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 0944E–12/01 PIN NO. 1 1.14(0.045) X 45˚ IDENTIFIER TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) AT17C512/010/LV512/010 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...
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