M51995AFP#CF0J Renesas Electronics America, M51995AFP#CF0J Datasheet - Page 39
M51995AFP#CF0J
Manufacturer Part Number
M51995AFP#CF0J
Description
IC SWIT PWM SMPS OVP UVLO 20SOIC
Manufacturer
Renesas Electronics America
Datasheet
1.M51995AFPCF0J.pdf
(43 pages)
Specifications of M51995AFP#CF0J
Output Isolation
Isolated
Frequency Range
170 ~ 207kHz
Voltage - Input
9.9 ~ 36 V
Power (watts)
1.5W
Operating Temperature
-30°C ~ 85°C
Package / Case
20-SOIC (0.200", 5.30mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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M51995AP/AFP
DET Circuit
Figure 41 shows how to use the DET circuit for the voltage detector and error amplifier.
For the phase shift compensation, it is recommended to connected the CR network between DET terminal and F/B
terminal.
Figure 42 shows the gain-frequency characteristics between point B and point C shown in figure 41.
The G1, ω
At the start of the operation, there happen to be no output pulse due to F/B terminal current through C1 and C2, as the
potential of F/B terminal rises sharply just after the start of the operation.
Not to lack the output pulse, is recommended to connect the capacitor C4 as shown by broken line.
Please take notice that the current flows through the R1 and R2 are superposed to I
connected to C
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 37 of 40
G1 =
ω
ω
Figure 42 Gain-Frequency Characteristics between Point B and C shown in Figure 41
1
2
1
=
=
and ω
C2 • R3
C1 • C2 • R3
R1 / R2
VCC2
C1 + C2
R3
1
2
are given by following equations;
as shown in figure 25.
………………………… (13)
Figure 41 How to use the DET Circuit for the Voltage Detector
……………………… (12)
………………… (14)
M51995A
G1
Log ω
DET
F/B
C
G
(DC Voltage gain)
ω
C4
1
C2
AVDET
C1
R3
ω
2
R1
R2
A
B
Detecting
voltage
CC(START)
. Not to superpose, R1 is