NCP1015ST100T3G ON Semiconductor, NCP1015ST100T3G Datasheet - Page 8

• Manufacturer Part Number: NCP1015ST100T3G
• Description: IC OFFLINE SWIT SMPS CM SOT223
• Manufacturer: ON Semiconductor

Specifications of NCP1015ST100T3G

• Output Isolation: Isolated
• Frequency Range: 90 ~ 110kHz
• Voltage - Input: 8.5 ~ 10 V
• Voltage - Output: 700V
• Power (watts): 19W
• Operating Temperature: 0°C ~ 150°C
• Package / Case: TO-261-4, TO-261AA, SOT-223-4
• Duty Cycle (max): 72 %
• Mounting Style: SMD/SMT
• Switching Frequency: 1000 KHz
• Operating Supply Voltage: - 0.3 V to + 10 V
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 60 C
• Operating Temperature (max): 150C
• Pin Count: 3 +Tab
• Mounting: Surface Mount
• Package Type: SOT-223
• Case Length: 6.5mm
• Case Height: 1.57mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

offer an adequate startup time, i.e. ensure regulation is
reached before V
the fault condition mode). If we know that DV = 1 V and
ICC1 is 1.2 mA (for instance we selected a 11 W device
switching at 65 kHz), then the V
calculated using:
we will calculate C to offer a 15 ms period. As a result, C
should be greater than 18 mF thus the selection of a 33 mF /
16 V capacitor is appropriate.
Short Circuit Protection
arrangement that permanently monitors the assertion of an
internal error flag. This error flag is, in fact, a signal that
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (V
when the optocoupler LED is no longer biased, e.g in a
short−circuit condition or when the feedback network is
broken. When the DSS normally operates, the logic checks
for the presence of the error flag every time V
V
the IC works normally. If the error signal is active, then the
NCP1015 immediately stops the output pulses, reduces its
internal current consumption and does not allow the startup
source to activate: V
CC(on)
As one can see, the V
Let’s suppose that the SMPS needs 10 ms to startup, then
The internal protection circuitry involves a patented
. If the error flag is low (peak limit not active) then
CC
out
C w
CC
crosses 7.5 V (otherwise the part enters
is not stabilized to the target value) or
CC
drops toward ground until it reaches
ICC1 @ t
8.00
6.00
4.00
2.00
Figure 13. The Charge/Discharge Cycle over a 10 mF V
capacitor shall be dimensioned to
0
DV
startup
Startup period
CC
Vcc
Device
internally
pulses
capacitor can be
8.5V
CC
crosses
(eq. 1)
http://onsemi.com
8
7.5V
the so−called latch−off level, where the current source
activates again to attempt a new re−start. If the error has
gone, the IC automatically resumes its operation. If the
default is still there, the IC pulses during 8.5 V down to 7.5 V
and enters a new latch−off phase. The resulting burst
operation guarantees a low average power dissipation and
lets the SMPS sustain a permanent short−circuit. Figure 14
presents the corresponding diagram:
through the various timing events as portrayed by Figure 15:
FB
The protection burst duty−cycle can easily be computed
4 V
Figure 14. Simplified NCP1015 Short−Circuit
Division
Active?
Clamp
Max
Ip
CC
Detection Circuitry
Capacitor
Current Sense
V
Information
CC
Flag
V
CC(on)
+
−
Reset
Latch
To