ICE3BS02 Infineon Technologies, ICE3BS02 Datasheet - Page 11

• Manufacturer Part Number: ICE3BS02
• Description: IC OFFLINE CTRLR SMPS CM 8DIP
• Manufacturer: Infineon Technologies
• Series: CoolSET®F3r

Specifications of ICE3BS02

• Output Isolation: Isolated
• Frequency Range: 61 ~ 73kHz
• Voltage - Input: 8.5 ~ 22 V
• Voltage - Output: 500V
• Power (watts): 900mW
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Outputs: 1
• Duty Cycle (max): 77 %
• Output Voltage: - 0.3 V to + 22 V
• Output Current: 700 mA
• Mounting Style: Through Hole
• Switching Frequency: 67 KHz
• Maximum Operating Temperature: + 130 C
• Fall Time: 55 ns
• Minimum Operating Temperature: - 25 C
• Rise Time: 150 ns
• Synchronous Pin: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ICE3BS02X; ICE3BS02XK; SP000014966

3.5
Figure 10
There is a cycle by cycle Current Limiting realized by the
Current-Limit comparator C10 to provide an overcurrent
detection. The source current of the external Power Switch is
sensed via an external sense resistor R
R
V
exceeds the internal threshold voltage V
C10 immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation is
added to support the immediate shut down without delay of
the Power Switch in case of Current Limiting. The influence
of the AC input voltage on the maximum output power can
thereby be avoided.
To prevent the Current Limiting from distortions caused by
leading edge spikes a Leading Edge Blanking is integrated in
the current sense path for the comparators C10, C12 and the
PWM-OP.
The output of comparator C12 is activated by the Gate G10
if Active Burst Mode is entered. Once activated the current
limiting is thereby reduced to 0.257V. This voltage level
determines the power level when the Active Burst Mode is
left if there is a higher power demand.
Version 1.2
Sense
Sense
PWM Latch
FF1
PWM-OP
the source current is transformed to a sense voltage
which is fed into the pin CS. If the voltage V
Active Burst
Mode
G10
Current Limiting
&
Current Limiting Block
Propagation-Delay
Compensation
CS
C10
C12
10k
0.257V
V
D1
csth
Sense
csth
Current Limiting
the comparator
. By means of
Blanking
Leading
220ns
Edge
1pF
ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G
Sense
11
3.5.1
Figure 11
Each time when the external Power Switch is switched on, a
leading edge spike is generated due to the primary-side
capacitances and secondary-side rectifier reverse recovery
time. This spike can cause the gate drive to switch off
unintentionally. To avoid a premature termination of the
switching pulse, this spike is blanked out with a time
constant of t
not be switched off.
3.5.2
In case of overcurrent detection, the switch-off of the
external Power Switch is delayed due to the propagation
delay of the circuit. This delay causes an overshoot of the
peak current I
peak current (see Figure 12).
Figure 12
The overshoot of Signal2 is bigger than of Signal1 due to the
steeper rising waveform. This change in the slope is
depending on the AC input voltage. Propagation Delay
Compensation is integrated to limit the overshoot
dependency on dI/dt of the rising primary current. That
means the propagation delay time between exceeding the
current sense threshold V
external Power Switch is compensated over temperature
within a wide range.
I
I
I
peak2
peak1
Limit
V
csth
I
V
Sense
Sense
LEB
Propagation Delay Compensation
Leading Edge Blanking
peak
Leading Edge Blanking
Current Limiting
I
= 220ns. During this time, the gate drive will
Overshoot2
which depends on the ratio of dI/dt of the
Signal1
csth
t
Functional Description
LEB
= 220ns
and the switch off of the
Signal2
t
Propagation Delay
02 Sep 2005
I
Overshoot1
t
F3
t