ISL9206ADRTZ-T Intersil, ISL9206ADRTZ-T Datasheet - Page 12

• Manufacturer Part Number: ISL9206ADRTZ-T
• Description: IC AUTHENTICATION DEVICE 8-TDFN
• Manufacturer: Intersil
• Series: FlexiHash+™r

Specifications of ISL9206ADRTZ-T

• Function: Battery Authentication
• Battery Type: Li-Ion, Li-Pol, NiMH
• Voltage - Supply: 2.6 V ~ 4.8 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERNAL VOLTAGE REGULATOR
The ISL9206A incorporates an internal voltage regulator that
maintains a nominal operating voltage of 2.5V within the
device. The regulator draws power directly from the VDD
input. No external component is required to regulate circuit
voltage. The regulator is shut off during Sleep mode.
Memory/Operational Register Description
The ISL9206A memory and register structure is organized
into 4 banks of 256 addressable locations. However, not all
of the addressable registers are used nor implemented.
Accessing an unimplemented register will result in the
access instruction being ignored. A bus error indication may
or may not be flagged.
Bank 0 is dedicated for the OTP ROM. There are 16 memory
locations implemented in the array. Writing to the OTP ROM
has no immediate effect on the chip operation until a
NOTE: Information stored in address 0-0E (INF1) and 0-0F (INF2) is for use by the host firmware only. Actual content depends on the host firmware
customization preference.
ADDRESS
ADDRESS
0-0C
0-0D
0-00
0-01
0-02
0-03
0-04
0-05
0-06
0-07
0-08
0-09
0-0A
0-0B
0-0E
0-0F
1-00
1-01
NAME
DTRM
DCFG
NAME
MSCR
SE1C
SE1D
SE2C
SE2D
SE3C
SE3D
SE1A
SE1B
SE2A
SE2B
SE3A
SE3B
STAT
INF1
INF2
12
Default Configuration
Default Trimming
General Purpose
General Purpose
Auth Secret #1A
Auth Secret #1B
Auth Secret #1C
Auth Secret #1D
Auth Secret #2A
Auth Secret #2B
Auth Secret #2C
Auth Secret #2D
Auth Secret #3A
Auth Secret #3B
Auth Secret #3C
Auth Secret #3D
DESCRIPTION
DESCRIPTION
Master Control
Device Status
TABLE 9. CONTROL AND STATUS REGISTERS (BANK 1)
TABLE 8. OTP ROM MEMORY MAP (BANK 0)
General purpose non-volatile memory for storage of model ID, date code, and other
eEEW
sEEW
BIT 7
BIT 7
HSF
ISL9206A
DAB[1:0]
BIT 6
sBER
BIT 6
eINT
Power-on Reset occurs, or a soft reset is issued. Table 7
describes the OTP ROM memory assignment. The default
factory setting for address [0:00] is given in Table 11.
Bank 1 contains the Control and Status registers. Only 2
registers are implemented. Table 8 shows the register map
of the Bank 1 registers. Detailed descriptions of register
settings are given in Tables 14 and 15.
Bank 2 contains the Authentication registers. Only 3
registers are implemented. These registers are used during
the battery pack authentication process. Table 10 describes
the mapping of the Authentication registers.
Bank 3 is reserved for Intersil production testing only and will
not be accessible during normal operation. Accessing the
Test and Trim Registers when not in test mode will result in a
bus error.
TIBB[2:0]
BIT 5
sACC
BIT 5
--
SPD[1:0]
BIT 4
BIT 4
cell information
--
--
S1C[7:0]
S1D[7:0]
S2C[7:0]
S2D[7:0]
S3C[7:0]
S3D[7:0]
S1A[7:0]
S1B[7:0]
S2A[7:0]
S2B[7:0]
S3A[7:0]
S3B[7:0]
BIT3
eINT
BIT3
--
DAB[1:0]
BIT 2
ASLP
BIT 2
--
TOSC[3:0]
BIT 1
ASLP
BIT 1
SLO[1:0]
SLO[1:0]
July 30, 2008
SRST
BIT 0
BIT 0
FN6651.1