MAX6962ATH+T Maxim Integrated Products, MAX6962ATH+T Datasheet - Page 23
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MAX6962ATH+T
Manufacturer Part Number
MAX6962ATH+T
Description
IC DRVR LED 8X8 44-TQFN
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX6963ATH.pdf
(35 pages)
Specifications of MAX6962ATH+T
Display Type
LED
Configuration
8 x 8 (Matrix)
Interface
4-Wire Serial
Digits Or Characters
Any Digit Type
Current - Supply
7.5mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
44-TQFN Exposed Pad
Number Of Segments
64
Low Level Output Current
750 mA
High Level Output Current
48 mA
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Supply Current
9 mA
Maximum Power Dissipation
2162 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 25. Digit 0 Intensity Register Format
Table 26. Digit 1 Intensity Register Format
The current plane bits in the global panel configuration
register identify which memory plane is currently being
used to control the display panel (Table 18). These bits
are read only; written data is ignored.
The ripple sync feature, when enabled in the global panel
configuration register, desynchronizes the multiplex timing
of all the interconnected MAX6960 drivers on a display
panel by OSC/4 (Table 19). This delay spreads the drive
transitions among the drivers to spread power-supply
peak-current demand, and ease decoupling. The maxi-
mum delay from first driver to last driver is 244µs with the
maximum of 256 drivers used. This is too short a time to
cause visible artifacts.
255/256 (max on)
255/256 (max on)
Current Plane Identification (Bits D2, D3)
REGISTER
REGISTER
251/256
252/256
253/256
254/256
251/256
252/256
253/256
254/256
0/256
1/256
2/256
3/256
4/256
0/256
1/256
2/256
3/256
4/256
—
—
______________________________________________________________________________________
Ripple Sync (Bit D4)
8 x 8 Matrix Graphic LED Drivers
ADDRESS CODE
CODE (HEX)
ADDRESS
(HEX)
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
4-Wire Serially Interfaced
D7
D7
—
—
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
The mux flip feature in the global panel configuration reg-
ister reverses the panel PWM timing for alternate drivers
when enabled (Table 20). Again, this spreads power-sup-
ply peak-current demand.
The color control bit in the global panel configuration reg-
ister selects whether a monocolor or RGY display panel is
built. Select monocolor when building an RGB panel as
shown in Figure 17. This bit is fixed at zero for the
MAX6962 and MAX6963, and a write to this bit is ignored
for these parts.
D6
D6
—
—
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
D5
D5
—
—
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
REGISTER DATA
REGISTER DATA
D4
—
D4
—
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
D3
—
D3
0
0
0
0
0
1
1
1
1
1
—
0
0
0
0
0
1
1
1
1
1
Color Control (Bit D6)
D2
—
D2
0
0
0
0
1
0
1
1
1
1
—
0
0
0
0
1
0
1
1
1
1
Mux Flip (Bit D5)
D1
—
D1
0
0
1
1
0
1
0
0
1
1
—
0
0
1
1
0
1
0
0
1
1
D0
—
D0
0
1
0
1
0
1
0
1
0
1
—
0
1
0
1
0
1
0
1
0
1
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