ADE7758ARWZ Analog Devices Inc, ADE7758ARWZ Datasheet - Page 24

• Manufacturer Part Number: ADE7758ARWZ
• Description: IC ENERGY METERING 3PHASE 24SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7758ARWZ

• Input Impedance: 380 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 8mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• Ic Function: Poly Phase Multifunction Energy Metering IC
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SOIC
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7758
The errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE7758 provides a
means of digitally calibrating these small phase errors. The
ADE7758 allows a small time delay or time advance to be
introduced into the signal processing chain to compensate for
the small phase errors.
The phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) are twos complement, 7-bit sign-extended registers
that can vary the time advance in the voltage channel signal
path from +153.6 μs to −75.6 μs (CLKIN = 10 MHz),
respectively. Negative values written to the PHCAL registers
represent a time advance, and positive values represent a time
delay. One LSB is equivalent to 1.2 μs of time delay or 2.4 μs of
time advance with a CLKIN of 10 MHz. With a line frequency
of 60 Hz, this gives a phase resolution of 0.026° (360° × 1.2 μs ×
60 Hz) at the fundamental in the positive direction (delay) and
0.052° in the negative direction (advance). This corresponds to
a total correction range of −3.32° to +1.63° at 60 Hz.
Figure 56 illustrates how the phase compensation is used to
remove a 0.1° phase lead in IA of the current channel from the
external current transducer. To cancel the lead (0.1°) in the
current channel of Phase A, a phase lead must be introduced
into the corresponding voltage channel. The resolution of the
phase adjustment allows the introduction of a phase lead of
0.104°. The phase lead is achieved by introducing a time
advance into VA. A time advance of 4.8 μs is made by writing
−2 (0x7E) to the time delay block (APHCAL[6:0]), thus
reducing the amount of time delay by 4.8 μs or equivalently,
360° × 4.8 μs × 60 Hz = 0.104° at 60 Hz.
Figure 53. Phase Response of the HPF and Phase Compensation
90
80
70
60
50
40
30
20
10
0
0
100
200
300
(10 Hz to 1 kHz)
FREQUENCY (Hz)
400
500
600
700
800
900
1k
Rev. D | Page 24 of 72
–0.05
–0.10
Figure 54. Phase Response of the HPF and Phase Compensation
–0.02
0.20
0.15
0.10
0.05
0.10
0.08
0.06
0.04
0.02
Figure 55. Phase Response of HPF and Phase Compensation
0
0
40
44
45
46
50
48
(40 Hz to 70 Hz)
(44 Hz to 56 Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
55
50
60
52
65
54
70
56