LTC4261IGN#PBF Linear Technology, LTC4261IGN#PBF Datasheet
LTC4261IGN#PBF
Specifications of LTC4261IGN#PBF
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LTC4261IGN#PBF Summary of contents
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... LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. Patents pending. All other trademarks are the property of their respective owners. ...
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LTC4261/LTC4261-2 ABSOLUTE MAXIMUM RATINGS V (Note 3) ......................................... –0.3V to 10.65V IN Drain (Note 4) .......................................... –0.3V to 3.5V PGI, ON, ALERT, SDAO, SDAI, SCL, ADIN, ADIN2, OV, SENSE, ADR1, ADR0, FLTIN, TMR, SS, RAMP Voltages .................... –0.3V to INTV ...
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ELECTRICAL CHARACTERISTICS temperature range, otherwise specifi cations are at I SYMBOL PARAMETER General V Shunt Regulator Voltage ΔV Shunt Regulator Load Regulation Supply Current Undervoltage Lockout Threshold IN(UVLO) IN ΔV ...
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LTC4261/LTC4261-2 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifi cations are at I SYMBOL PARAMETER Timer V TMR Pin High Threshold TMR(H) V TMR Pin Low Threshold TMR(L) I TMR Pin Pull-Up Current TMR(UP) I TMR Pin Pull-Down Current TMR(DN) Output Pins ...
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ELECTRICAL CHARACTERISTICS temperature range, otherwise specifi cations are at I SYMBOL PARAMETER Interface Timing (Note 5) f Maximum SCL Clock Frequency SCL(MAX) t Minimum SCL Low Period LOW t Minimum SCL High Period HIGH t Minimum Bus ...
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LTC4261/LTC4261-2 TYPICAL PERFORMANCE CHARACTERISTICS Shunt Regulator Voltage vs Input Current 10.8 11 11.2 11.4 11.6 SHUNT REGULATOR VOLTAGE AT V (V) IN 42612 G01 GATE Output High Voltage vs Temperature 10 ...
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TYPICAL PERFORMANCE CHARACTERISTICS OV Threshold vs Temperature 1.785 1.780 1.775 1.770 1.765 1.760 1.755 –50 – TEMPERATURE (°C) 42612 G08 Current Limit Propagation Delay ( PHL(SENSE) SENSE 1000 C = 1pF GATE 100 ...
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LTC4261/LTC4261-2 PIN FUNCTIONS (SSOP/QFN) ADIN (Pin 23/Pin 16): ADC Input. A voltage between 0V and 2.56V applied to this pin is measured by the on-chip ADC. Tie unused. EE ADIN2 (Pin 10/NA): Second ADC Input. Not available ...
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PIN FUNCTIONS (SSOP/QFN) PGIO (Pin 28/Pin 21): General Purpose Input/Output. Open- drain logic output and logic input. Defaults to pull low a timer delay after the PG pin goes low to indicate a second power good output. Confi gure according ...
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LTC4261/LTC4261-2 BLOCK DIAGRAM 11.2V UVLO INTV = 4.25V CC 10µA 50nA 3pF SSC UVL 2.291V UVH 2.56V OV 1.77V 5µA 5µA TMR 2.56V 12mA 5µA ADR0 8 A0 • • DECODER ADR1 A7 ...
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OPERATION The LTC4261/LTC4261-2 are designed to turn a board’s supply voltage on and off in a controlled manner, allow- ing the board to be safely inserted or removed from a live – 48V backplane. The devices also feature an onboard ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION The LTC4261/LTC4261-2 are ideally suited for –48V distributed power systems and AdvancedTCA systems. A basic 200W application circuit using the LTC4261 is shown in Figure 1. A more complete application circuit with AdvancedTCA connections is shown in ...
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APPLICATIONS INFORMATION the voltage 11. and provides power to the IN Z GATE driver. The data converter and logic control circuits are powered by an internal linear regulator that derives 5V from the 11.2V supply. ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION If any of the above conditions is violated before the start-up delay expires quickly discharged and the turn-on TMR sequence is restarted. After all the conditions are validated throughout the start-up delay, the ON pin ...
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APPLICATIONS INFORMATION RTN_V EE UVH START-UP DELAY TMR 1x SS GATE V OUT SENSE INTERNAL PWRGD PG PGIO PGI 6. The voltage at INTV is lower than 4.25V (INTV CC undervoltage lockout > 50mV and the condition lasts ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION EN and ON Figure 4 shows a logic diagram for EN and ON as they relate to GATE, ALERT and internal registers A4, A7, B4, C4 and D3. Also affecting GATE is the status of UV, OV ...
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APPLICATIONS INFORMATION OC COOLING DELAY TMR 4x SS GATE V OUT 50mV SENSE 530µs PG PGIO In the case of a low impedance short circuit on the load side or an input step during battery replacement, cur- rent overshoot is ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION RTN – TMR SS V GATE V OUT SENSE PG PGIO to turn on again immediately (without delay) unless the overvoltage auto-retry has been disabled by clearing reg- ister bit D0. Undervoltage Comparator and Undervoltage ...
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APPLICATIONS INFORMATION –48V RTN –48V RTN R3 R3 453k 453k 1% 1% UVL R R TURN-ON = 46V H H 1.91k 1.91k TURN-OFF = 38. HYSTERESIS = 7.5V UVH R2 R2 15k 15k ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION the lower address wins arbitration and responds fi rst. The ALERT line will also be released if the device is addressed by the bus master. Once the ALERT signal has been released for one fault, it will ...
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APPLICATIONS INFORMATION Ejector Switch or Loop-Through Connection Sense. Floating switch contacts or a connection sense loop also work well with the ON pin, replacing the phototransistor in Figure 8a insertion debounce delay is desired, use the EN pin ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION Confi guring the PGIO Pin Table 6 describes the possible states of the PGIO pin us- ing the CONTROL register bits D6 and D7. At power-up the default state is for the PGIO pin to pull low ...
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APPLICATIONS INFORMATION Interface The LTC4261/LTC4261-2 feature an I vide access to the ADC data registers and four other reg- isters for monitoring and control of the pass FET. Figure 9 shows a general data transfer format using ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION reset to allow normal communication after the stuck-low condition is cleared. When the SCL pin and the SDAI pin are held low alternatively, if the ORed low period of SCL and SDAI exceeds 66ms before the timer ...
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APPLICATIONS INFORMATION ALERT DEVICE S RESPONSE R A ADDRESS ADDRESS a3: Figure 14. LTC4261 Serial Bus SDA Alert Response Protocol Figure 14. LTC4261 Serial Bus SDA ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION (DMY) to measure the internal clock cycle (i.e., the serial data rate). Following the DMY bit are two channel code bits CH1 and CH0 labeling the ADC channel (see Table 10). Ten data bits of the ADC ...
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APPLICATIONS INFORMATION Table 1. LTC4261 Device Addressing HEX DEVICE DESCRIPTION ADDRESS h 6 Mass Write 3E 0 Alert Response ...
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LTC4261/LTC4261-2 APPLICATIONS INFORMATION Table 3. STATUS Register A (00h)—Read Only BIT NAME OPERATION A7 FET On Indicates State of FET FET On FET Off A6 PGIO Input Indicates State of the PGIO Pin when Confi gured ...
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APPLICATIONS INFORMATION Table 6. CONTROL Register D (03h)—Read/Write BIT NAME OPERATION D7:6 PGIO Confi gure Confi gures Behavior of PGIO Pin FUNCTION Power Good (Default) Power Good General Purpose Output General Purpose Input D5 Test Mode Enable Test Mode Halts ...
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LTC4261/LTC4261-2 PACKAGE DESCRIPTION .254 MIN .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT .0075 – .0098 (0.19 – 0.25) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE ...
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... ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. UFD Package 24-Lead Plastic QFN (4mm × ...
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... With I C and ADC, Supplies from 8.5V to 80V Controls Two N-Channel MOSFETs, 1µs Turn-Off, 80V Operation ● www.linear.com ANODE 330 MICRO- CATHODE V 100V OUT CONTROLLER GND R7 4261 F17 42612 F18 LT 0706 REV B • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2005 F 42612fb ...