PCA9514AD,112 NXP Semiconductors, PCA9514AD,112 Datasheet - Page 8

• Manufacturer Part Number: PCA9514AD,112
• Description: IC I2C/SMBUS BUFF 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: I²C-Bus and SMBus Switchr

Specifications of PCA9514AD,112

• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Applications: Hot-Swap/SMB Buffer
• Internal Switch(s): Yes
• Current Limit: 50mA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: PCA
• Supply Voltage (max): 7 V
• Supply Voltage (min): - 0.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Output Voltage: 0.3 V
• Propagation Delay Time: 80 ns
• Supply Current: 3.5 mA
• Logic Type: SMBus Bus Buffer
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: SO
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3365-5; 935279867112; PCA9514AD

NXP Semiconductors
PCA9513A_PCA9514A_4
Product data sheet
8.5 Rise time accelerators
8.6 READY digital output
8.7 ENABLE low current disable
8.8 Resistor pull-up value selection
The t
below 0.7V
maximum slew rate, and even if the input slew rate is slow enough that the output catches
up it will still lag the falling voltage of the input by the offset voltage. The maximum t
occurs when the input is driven LOW with zero delay and the output is still limited by its
turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function
of the internal maximum slew rate which is a function of temperature, V
well as the load current and the load capacitance.
During positive bus transitions a 2 mA current source is switched on to quickly slew the
SDA and SCL lines HIGH once the input level of 0.8 V for the PCA9513A and PCA9514A
are exceeded. The rising edge rate should be at least 1.25 V/ s to guarantee turn on of
the accelerators. The built-in V/ t rise time accelerators on all SDA and SCL lines
requires the bus pull-up voltage and supply voltage (V
This pin provides a digital flag which is LOW when either ENABLE is LOW or the start-up
sequence described earlier in this section has not been completed. READY goes HIGH
when ENABLE is HIGH and start-up is complete. The pin is driven by an open-drain
pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of
10 k to V
Grounding the ENABLE pin disconnects the backplane side from the card side, disables
the rise time accelerators, drives READY LOW, disables the bus precharge circuitry, and
puts the part in a low current state. When the pin voltage is driven all the way to V
part waits for data transactions on both the backplane and card sides to be complete
before reconnecting the two sides.
The system pull-up resistors must be strong enough to provide a positive slew rate of
1.25 V/ s on the SDAn and SCLn pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value using the formula given in
Equation
where R
and C is the equivalent bus capacitance in picofarads.
In addition, regardless of the bus capacitance, always choose R
V
requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the
card, and these pull-up values are needed to overcome the precharge voltage. See the
curves in
R
CC
PU
= 5.5 V maximum, R
PHL
800
PU
can never be negative because the output does not start to fall until the input is
1:
Figure 6
CC
CC
is the pull-up resistor value in , V
10
, and the output turn on has a non-zero delay, and the output has a limited
to provide the pull-up.
3
V
---------------------------------- -
and
CC min
Rev. 04 — 18 August 2009
Figure 7
C
PU
–
0.6
45 k for V
for guidance in resistor pull-up selection.
Hot swappable I
PCA9513A; PCA9514A
CC
= 3.6 V maximum. The start-up circuitry
CC(min)
is the minimum V
CC
) to be the same.
2
C-bus and SMBus bus buffer
PU
65.7 k for
CC
CC
© NXP B.V. 2009. All rights reserved.
and process, as
voltage in volts,
CC
PHL
8 of 26
, the
(1)