MIC2587R-1YM Micrel Inc, MIC2587R-1YM Datasheet - Page 3

• Manufacturer Part Number: MIC2587R-1YM
• Description: IC CTRLR HOTSWAP 1CHAN POS 8SOIC
• Manufacturer: Micrel Inc
• Type: Hot-Swap Controllerr

Specifications of MIC2587R-1YM

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 10 V ~ 80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Family Name: MIC2587
• Package Type: SOIC
• Operating Supply Voltage (min): 10V
• Operating Supply Voltage (max): 80V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.94mm
• Product Height (mm): 1.48mm
• Product Length (mm): 4.93mm
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1097

Pin Description
Micrel
October 2004
Pin Number
1
2
3
4
5
(MIC2587R-1)
(MIC2587R-2)
(MIC2587-1)
Active-HIGH
(MIC2587-2)
Active-LOW
Pin Name
/PWRGD
PWRGD
TIMER
GND
ON
FB
Pin Function
Enable Input: When the voltage at the ON pin is higher than the V
is initiated. An internal current source (I
ramping up the voltage at this pin to turn on an external MOSFET. Whenever the voltage at
the ON pin is lower than the V
and the I
internal current source (I
reset the circuit breaker then back HIGH (ON pin) will initiate another start cycle.
Output Voltage Feedback Input: This pin is connected to an external resistor divider that is
used to sample the output load voltage. The voltage at this pin is measured against an
internal comparator whose output controls the PWRGD (or /PWRGD) signal. PWRGD (or
/PWRGD) asserts when the FB pin voltage crosses the V
voltage is lower than its V
comparator exhibits a typical hysteresis of 80mV.
The FB pin voltage also affects the MIC2587/MIC2587R’s foldback current limit operation
(see the “Functional Description” section for further information).
Power-is-Good (PWRGD or /PWRGD), Open-drain Output: This pin remains de-asserted
during start up while the FB pin voltage is below the V
FB pin rises above the V
(typically ≤ 5µs).
For the (-1) options, the PWRGD output pin will be high-impedance when the FB pin voltage
is higher than V
For the (-2) options, the /PWRGD output pin will be high-impedance when the FB pin
voltage is lower than V
V
The Power-is-Good output pin is connected to an open-drain, N-channel transistor
implemented with high-voltage structures. These transistors are capable of operating with
pull-up resistors to supply voltages as high as 100V.
To use this signal as a logic control in low-voltage dc-dc conversion applications, an external
pull-up resistor between this pin and the logic supply voltage is recommended, unless an
internal pull-up impedance is provided by the dc-dc module or other device (load).
Tie this pin directly to the system’s analog GND plane
Current Limit Response Timer:
overcurrent filtering to prevent nuisance “tripping” of the circuit breaker by setting the time
(t
breaker trips, the output latches off. Under normal (steady state) operation, the TIMER pin
is held to GND by an internal 3.5µA current source (I
external sense resistor exceeds the V
(I
pin voltage reaches the V
low, the I
the I
MIC2587 can be restarted by toggling the ON pin LOW then HIGH.
For the MIC2587R, the capacitor connected to the TIMER pin sets the period of auto-retry
where the duty cycle is fixed at a nominal 5%.
FBH
FLT
TIMERUP
) for which the controller is allowed to remain in current limit. Once the MIC2587 circuit
.
TIMERDN
) is activated to charge the capacitor connected to the TIMER pin. When the TIMER
GATEON
TIMERUP
current source. When the voltage at the TIMER pin is less than 0.5V, the
current source is disabled while the GATE pin is pulled low by another
FBH
current source is disabled, and the TIMER pin capacitor is discharged by
and will pull down to GND when the FB pin voltage is less than V
FBL
GATEOFF
FBH
FBL
TIMERH
and will pull down to GND when the FB pin voltage is higher than
threshold, the Power-is-Good output asserts with minimal delay
threshold, PWRGD (or /PWRGD) is de-asserted. The FB
3
ONL
). After a load current fault, toggling the ON pin LOW will
threshold, the circuit breaker is tripped pulling the GATE pin
threshold, an undervoltage lockout condition is detected
A capacitor connected from this pin to GND provides
GATEON
TRIP
) is activated which charges the GATE pin,
threshold, an internal 65µA current source
FBH
TIMERDN
FBH
threshold. Once the voltage at the
). When the voltage across the
threshold. When the FB pin
ONH
threshold, a start cycle
MIC2587/MIC2587R
[phone]
M9999-102204
FBL
.