ISL6161CBZA Intersil, ISL6161CBZA Datasheet - Page 6

• Manufacturer Part Number: ISL6161CBZA
• Description: IC CTLR PWR DISTRIB DUAL 14SOIC
• Manufacturer: Intersil
• Type: Hot-Swap Controllerr

Specifications of ISL6161CBZA

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 10.5 V ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
NOTE: Nominal CR Vth = R
NOTE: Nominal time-out period in seconds = C
The ISL6161 responds to a load short (defined as a current
level 3x the OC set point with a fast transition) by
immediately driving the relevant N-Channel MOSFET gate to
0V in ~3µs. The gate voltage is then slowly ramped up,
soft-starting the N-Channel MOSFET to the programmed
current regulation limit level. This is the start of the time-out
period if the abnormal load condition still exists. The
programmed current regulation level is held until either the
OC event passes or the time-out period expires. If the former
is the case, then the N-Channel MOSFET is fully enhanced
and the C
capacitor. If the time-out period expires prior to OC
resolution, then both gates are quickly pulled to 0V turning
off both N-Channel MOSFETs simultaneously.
Upon any UV condition, the PGOOD signal will pull low
when tied high through a resistor to the logic supply. This pin
is a fault indicator but not the OC latch-off indicator. For an
OC latch-off indication, monitor CTIM, pin 10. This pin will
rise rapidly to 12V once the time-out period expires. See
“Simplified Schematic” on page 2 for OC latch-off circuit
suggestion.
The ISL6161 is reset by a rising edge on the ENABLE pin
and is turned on by the ENABLE pin being driven low.
PCI-EXPRESS
ADD-IN CARD
CONNECTOR
X4/X8
TABLE 1. R
X16
X1
C
TIM
TIM
CAPACITOR
0.022
0.047
(µF)
0.1
charging current is diverted away from the
SENSE
R
(kΩ)
4.99
4.99
4.99
ILIM
10
10
10
AND R
3.3V R
NOMINAL
ILIM
TABLE 2.
CR (A)
30, 3.3
15, 3.5
30, 3.3
15, 3.5
30, 3.3
15, 3.5
(mΩ),
x 10µA.
SENSE
ILIM
6
NOMINAL TIME-OUT PERIOD
RECOMMENDATIONS
12V R
NOMINAL
150, 0.7
CR (A)
90, 0.6
40, 2.5
20, 2.6
16, 6.3
(mΩ),
8, 6.6
SENSE
TIM
(ms)
4.4
9.4
20
x 200kΩ.
NOMINAL
CRVth
(mV)
100
100
100
53
53
53
ISL6161
ISL6161 Application Considerations
In a non PCI-Express, motor drive application, Current loop
stabilization is facilitated through a small value resistor in
series with the gate timing capacitor. As the ISL6161 drives
a highly inductive current load, instability characterized by
the gate voltage repeatedly ramping up and down may
appear. A simple method to enhance stability is provided by
the substitution of a larger value gate resistor. Typically, this
situation can be avoided by eliminating long point-to-point
wiring to the load.
With the ENABLE internal pull-up, the ISL6161 is well suited
for implementation on either side of the connector where a
motherboard prebiased condition or a load board staggered
connection is present. In either case, the ISL6161 turns on in
a soft-start mode protecting the supply rail from sudden
current loading.
During the Time-Out delay period with the ISL6161 in
current limit mode, the V
MOSFETs is reduced driving the N-Channel MOSFET switch
into a high r
periods as the external N-Channel MOSFETs may be
damaged or destroyed due to excessive internal power
dissipation. Refer to the MOSFET manufacturers data sheet
for SOA information.
With the high levels of in-rush current e.g., highly capacitive
loads and motor start-up currents, choosing the current
regulation (CR) level is crucial to provide both protection
and still allow for this in-rush current without latching off.
Consider this in addition to the time-out delay when
choosing MOSFETs for your design.
Physical layout of R
inadvertently lowering the CR and trip levels. Ideally, trace
routing between the R
should be as direct and as short as possible with zero
current in the sense lines.
TO ISEN AND
CORRECT
R
ISET
FIGURE 1. SENSE RESISTOR PCB LAYOUT
DS(ON)
state. Thus, avoid extended time-out
SENSE RESISTOR
SENSE
SENSE
GS
CURRENT
of the external N-Channel
resistors is critical to avoid
resistors and the ISL6161
INCORRECT
October 2, 2008
FN9104.4