LTC4253CGN#PBF Linear Technology, LTC4253CGN#PBF Datasheet - Page 19
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LTC4253CGN#PBF
Manufacturer Part Number
LTC4253CGN#PBF
Description
IC HOT SWAP CONTRLR -48V 16-SSOP
Manufacturer
Linear Technology
Type
Hot-Swap Controllerr
Datasheet
1.LTC4253CGNPBF.pdf
(34 pages)
Specifications of LTC4253CGN#PBF
Applications
General Purpose
Internal Switch(s)
No
Voltage - Supply
11.2 V ~ 14.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SSOP (0.150", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
applicaTions inForMaTion
Sense
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to V
SENSE exceeds 50mV, the CB comparator activates the
200µA TIMER pull-up. At 100mV (60mV for the LTC4253A)
the ACL amplifier servos the MOSFET current, and at
200mV the FCL comparator abruptly pulls GATE low in
an attempt to bring the MOSFET current under control. If
any of these conditions persists long enough for TIMER to
charge C
shut down and pull GATE low.
If the SENSE pin encounters a voltage greater than V
the ACL amplifier will servo GATE downwards in an attempt
to control the MOSFET current. Since GATE overdrives the
MOSFET in normal operation, the ACL amplifier needs time
to discharge GATE to the threshold of the MOSFET. For a
mild overload the ACL amplifier can control the MOSFET
current, but in the event of a severe overload the current
may overshoot. At SENSE = 200mV the FCL comparator
takes over, quickly discharging the GATE pin to near V
potential. FCL then releases, and the ACL amplifier takes
over. All the while TIMER is running. The effect of FCL is
to add a nonlinear response to the control loop in favor
of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop, and GATE undershoots.
A zero in the loop (resistor R
capacitor) helps the ACL amplifier to recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load side low impedance
short is shown in Figure 5. Initially the current overshoots
the analog current limit level of V
as the GATE pin works to bring V
The overshoot glitches the backplane in the negative direc-
tion and when the current is reduced to 100mV/R
backplane responds by glitching in the positive direction.
T
to 4V (see Equation 3), the LTC4253/LTC4253A
C
GS
SENSE
in series with the gate
under control (trace 3).
= 200mV (trace 2)
EE
. When
S
, the
ACL
EE
,
TIMER commences charging C
current limit loop maintains the fault current at 100mV/R
which in this case is 5A (trace 2). Note that the backplane
voltage (trace 1) sags under load. Timer pull-up is accel-
erated by V
PWRGD signals pull high, the load current drops to zero
and the backplane rings up to over 100V. The transient
associated with the GATE turn-off can be controlled with
a snubber to reduce ringing and a transient voltage sup-
pressor (such as Diodes Inc. SMAT70A) to clip off large
spikes. The choice of RC for the snubber is usually done
experimentally. The value of the snubber capacitor is usu-
ally chosen between 10 to 100 times the MOSFET C
The value of the snubber resistor is typically between 3Ω
to 100Ω.
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The ini-
tial glitch and backplane sag as seen in Figure 5 trace 1,
can rob charge from output capacitors on the adjacent
card. When the faulty card shuts down, current flows in
to refresh the capacitors. If LTC4253/LTC4253A are used
by the other cards, they respond by limiting the inrush
current to a value of V
capacitors will recharge long before C
Figure 5. Output Short-Circuit Behavior of LTC4253
–48RTN
200mV
SENSE
0.5ms
0.5ms
0.5ms
0.5ms
TIMER
GATE
50V
10V
OUT
5V
. When C
TO CURRENT OVERSHOOT
LTC4253/LTC4253A
SUPPLY RING OWING
ACL
ONSET OF OUTPUT
SHORT-CIRCUIT
T
FAST CURRENT
LIMIT
ANALOG
CURRENT LIMIT
/R
reaches 4V, GATE turns off, the
C
TIMER
S
. If C
T
RAMP
(trace 4) while the analog
SUPPLY RING OWING
TO MOSFET TURN-OFF
T
is sized correctly, the
LATCH OFF
T
times out.
4253 F05
TRACE 1
TRACE 2
TRACE 3
TRACE 4
19
425353afd
OSS
S
,
.