LT4254IGN#TRPBF Linear Technology, LT4254IGN#TRPBF Datasheet - Page 13

• Manufacturer Part Number: LT4254IGN#TRPBF
• Description: IC CTLR HOTSWAP POS 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LT4254IGN#TRPBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 10.8 V ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Family Name: LT4254
• Package Type: SSOP N
• Operating Supply Voltage (min): 10.8V
• Operating Supply Voltage (max): 36V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LT4254 stays in current limit long enough for the TIMER
pin to fully charge up to its threshold, the LT4254 will
either latch off (RETRY = 0) or go into the current limit
hiccup mode (RETRY = floating). In either case, an open
FET condition will be falsely signalled. If the LT4254 does
go into current limit during start-up, C1 can be increased
(see Power-Up Sequence).
Supply Transient Protection
The LT4254 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 44V. However,
voltage transients above 44V may damage the part.
During a short-circuit condition, the large change in
currents flowing through the power supply traces can
cause inductive voltage transients which could exceed
44V. To minimize the voltage transients, the power trace
parasitic inductance should be minimized by using wider
traces or heavier trace plating and a 0.1µF bypass capaci-
tor should be placed between V
Figure 12. Delay Circuit for OPEN FET Detection
OPEN COLLECTOR
PULL-DOWN
INTERNAL
LT4254
U
GND
V
CC
V
LOGIC
4
U
R
OPEN
0.1µF
(SHORT PIN)
C3
CC
4254 F12
C
W
Figure 11. Active Low Enable PWRGD Application
and GND. A surge
R1
324k
R2
40.2k
R3
40.2k
TO
MONITORING
LOGIC
C2
33nF
1
2
4
9
UV
OV
OPEN
TIMER
U
V
CC
16
100mΩ
LT4254
GND
R5
8
SENSE
PWRGD
RETRY
GATE
15
FB
13
10
7
5
suppressor (Transorb) at the input can also prevent
damage from voltage transients.
GATE Pin
A curve of gate drive vs V
GATE pin is clamped to a maximum voltage of 12V above
the V
internal charge pump current. An external zener diode
should be used if the possibility exists for an instanta-
neous low resistance short on V
mum input supply voltage of 12V, the minimum gate drive
voltage is 4.5V. When the input supply voltage is higher
than 20V, the gate drive voltage is at least 10V and a
IRF530
UV = 20V
OV = 40V
PWRGD = 18V
Q1
R7
100Ω
R9
40.2k
R6
10Ω
CC
C1
10nF
voltage. This clamp is designed to withstand the
D1
CMPZ5241B
11V
12
11
10
9
8
7
6
5
4
140k
10
R8
Figure 13. ∆V
4254 F11
R4
27k
20
Q2
R10
27k
V
CC
CC
PWRGD
∆V
C
(V)
L
is shown in Figure 13. The
GATE
30
GATE
V
V
OUT
LOGIC
OUT
= V
vs V
GATE
to occur. At a mini-
CC
40
– V
4254 F13
CC
LT4254
13
4254fb