LT4254IGN#TRPBF Linear Technology, LT4254IGN#TRPBF Datasheet - Page 14

• Manufacturer Part Number: LT4254IGN#TRPBF
• Description: IC CTLR HOTSWAP POS 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LT4254IGN#TRPBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 10.8 V ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Family Name: LT4254
• Package Type: SSOP N
• Operating Supply Voltage (min): 10.8V
• Operating Supply Voltage (max): 36V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LT4254
standard threshold MOSFET can be used. In applications
from 12V to 15V range, a logic level MOSFET must be
used.
In some applications it may be possible for the V
ring below ground (due to the parasitic trace inductance).
Higher current applications, especially where the output
load is physically far away from the LT4254 will be more
susceptible to these transients. This is normal and the
LT4254 has been designed to allow for some ringing
below ground. However, if the application is such that
V
occur to the LT4254 and an external diode from ground
(anode) to V
circuit as shown in Figure 14 (it is critical that the reverse
breakdown voltage of the diode be higher than the highest
expected V
V
amount of ringing on V
some applications.
During a fault condition, the LT4254 pulls down on the
GATE pin with a switch capable of sinking about 55mA.
Once the GATE voltage drops below the output voltage by
a diode forward voltage, the external zener will forward
bias and the output will also be discharged to GND. In
addition to the GATE capacitance, the output capacitance
will be discharged through the LT4254. In applications
14
OUT
OUT
can ring more than 1V below ground, damage may
directly at the LT4254 pins can help reduce the
CC
OUT
voltage). A capacitor placed from ground to
(cathode) will have to be added to the
U
GND
V
CC
OUT
U
0.1µF
but it may not be enough for
(SHORT PIN)
C3
Figure 14. Negative Output Voltage Protection Diode Application
W
R1
324k
R2
40.2k
R3
40.2k
C2
33nF
1
2
4
9
UV
OV
OPEN
TIMER
U
OUT
V
CC
16
0.033Ω
LT4254
GND
R5
pin to
8
SENSE
PWRGD
RETRY
GATE
15
FB
13
10
7
5
that have very large output capacitors, this could cause
damage to the LT4254. Therefore, the maximum output
capacitance that can be used with the LT4254 is 1000µF.
In applications utilizing very large external N-channel
MOSFETs, the possibility exists for the MOSFET to turn on
when initially inserted into a live backplane (before the
LT4254 becomes active and pulls down on GATE). This is
due to the drain to gate capacitance forcing current into R7
and C1 when the drain voltage steps up from ground to V
with an extremely fast rise time. To alleviate this situation,
a Schottky diode should be put across R7 with the cathode
connected to C1 as shown in Figure 16.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
to the current sense resistor (R5 in typical application
circuit) is recommended. The minimum trace width for
1oz copper foil is 0.02" per amp to make sure the trace
stays at a reasonable temperature. 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/ . Small resistances can cause
large errors in high current applications. Noise immunity
will be improved significantly by locating resistor dividers
close to the pins with short V
decoupling capacitor from UV to GND is also required.
Figure 15 shows a layout that meets these requirements.
IRF530
Q1
UV = 20V
OV = 40V
PWRGD = 18V
R7
100Ω
R6
10Ω
C1
10nF
D1
CMPZ5241B
11V
R9
40.2k
R8
140k
4254 F14
R4
27k
MRA4003T3
C
100µF
CC
L
V
OUT
and GND traces. A 0.1µF
4254fb
CC