LTC4214-1CMS Linear Technology, LTC4214-1CMS Datasheet - Page 19

• Manufacturer Part Number: LTC4214-1CMS
• Description: IC CTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4214-1CMS

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 6 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
tween the compensation capacitor C
C
for C
mized values for C
MOSFETs. Differences in the optimized value of C
the starting value are small. Nevertheless, compensation
values should be verified by board level short-circuit
testing.
As seen in Figure 5 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
cally owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4214’s
V
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4214 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
ISS
EE
. The line in Figure 6 is used to select a starting value
and SENSE pins are strongly recommended. The
C
based upon the MOSFET’s C
15
25
20
10
Figure 6. Recommended Compensation
Capacitor C
5
0
0
IRF7803
1000
•
•
IRF7413
Si4412ADY
U
2000
•
C
C
MOSFET, C
vs MOSFET C
are shown for several popular
3000
U
Si4410DY
•
4000 5000
ISS
Si4864DY
(pF)
ISS
ISS
W
Si4876DY
C
•
6000 7000
specification. Opti-
and the MOSFET’s
•
4214 F06
U
C
versus
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
V
exceeds V
OV < V
and TIMER < V
timing cycle starts and the TIMER capacitor is charged by
a 5 A current source pull-up. At time point 3, TIMER
reaches the V
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the V
conditions of GATE < V
SS < 20 • V
cycle begins. SS ramps up as dictated by R
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 • V
GATE, 50 A sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
V
TRACK WIDTH W:
ON 1 OZ COPPER
IN
ACL
0.03" PER AMP
, V
Figure 7. Making PCB Connections to the Sense Resistor
(t) (Equation 7) and soft-start limits the slew rate of
OUT
OVHI
CURRENT FLOW
, DRAIN and PWRGD. At time point 2, V
LKO
FROM LOAD
, GATE < V
OS
LTC4214-1/LTC4214-2
and the internal logic checks for UV > V
TMRH
W
must be satisfied before a GATE ramp-up
TMRL
threshold and the initial timing cycle
TMRL
. If all conditions are met, an initial
GATEL
SENSE
SENSE RESISTOR
TO
threshold is reached and the
, SENSE < V
GATEL
V
TO
, SENSE < V
EE
OS
TO –12V BACKPLANE
CB
CURRENT FLOW
. Upon releasing
, SS < 20 • V
SS
• C
SS
19
CB
4214 F07
(as in
UVHI
421412f
and
OS
IN
,