LTC4214-1CMS Linear Technology, LTC4214-1CMS Datasheet - Page 20

• Manufacturer Part Number: LTC4214-1CMS
• Description: IC CTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4214-1CMS

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 6 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC4214-1/LTC4214-2
the load current. If the SENSE voltage (V
reaches the V
breaker TIMER activates. The TIMER capacitor, C
charged by a (40 A + 8 • I
capacitor nears full charge, load current begins to decline.
At time point 8, the load current falls and the SENSE
voltage drops below V
shuts off and the GATE pin ramps further. At time point 9,
the SENSE voltage drops below V
ends, followed by a 5 A discharge cycle (cool off). The
duration between time points 7 and 9 must be shorter than
one circuit breaker delay to avoid a fault time out during
20
GND – (–12V)
PWRGD
SENSE
UV/OV
TIMER
DRAIN
GATE
V
OUT
V
SS
CB
IN
threshold at time point 7, the circuit
U
1
ACL
V
2
IN
V
V
CLEARS V
DRN
(t). The analog current limit loop
GATEL
LKO
U
Figure 8. System Power-Up Timing (All Waveforms are Referenced to V
) current pull-up. As the load
LKO
CB
, CHECK UV > V
5 A
, the fault TIMER cycle
W
INITIAL TIMING
UVHI
SENSE
, OV < V
U
20 • (V
20 • (V
V
TMRH
– V
OVHI
ACL
CB
20 • V
T
, is
V
+ V
+ V
EE
, GATE < V
TMRL
OS
OS
OS
)
)
)
50 A
3 4 56
TIMER CLEARS V
40 A + 8 • I
GATEL
GATE ramp-up. When GATE ramps past the V
old at time point 10, PWRGD pulls low. At time point 11,
GATE reaches its maximum voltage as determined by V
Live Insertion with Short Pin Control of UV/OV
In the example shown in Figure 9, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4214 is
activated. At time point 1, the power pins make contact and
V
IN
START-UP
, SENSE < V
ramps through V
GATE
7
50 A
DRN
8
9
10 11
TMRL
CB
, SS < 20 • V
, CHECK GATE < V
V
V
V
V
V
IN
ACL
CB
DRNCL
DRNL
– V
GATEH
5 A
LKO
OS
AND TIMER < V
. At time point 2, the UV/OV divider
GATEL
, SENSE < V
EE
)
TMRL
5 A
CB
AND SS < 20 • V
4214 F08
GATEH
OS
thresh-
421412f
IN
.