LTC4214-2CMS#TRPBF Linear Technology, LTC4214-2CMS#TRPBF Datasheet - Page 22

• Manufacturer Part Number: LTC4214-2CMS#TRPBF
• Description: IC CTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4214-2CMS#TRPBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 6 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Linear Misc Type: Negative Low Voltage
• Family Name: LTC4214-2
• Package Type: MSOP
• Operating Supply Voltage (min): -6V
• Operating Supply Voltage (max): -16V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
(40 A + 8 • I
nears full charge, load current begins to decline. At point
8, the load current falls and the SENSE voltage drops below
V
GATE pin ramps further. At time point 9, the SENSE voltage
drops below V
by a 5 A discharge cycle (cool off). When GATE ramps
past V
At time point 11, GATE reaches its maximum voltage as
determined by V
LTC4214-1/LTC4214-2
22
ACL
(t). The analog current limit loop shuts off and the
GATEH
PWRGD
SENSE
TIMER
DRAIN
GATE
threshold at time point 10, PWRGD pulls low.
UV
SS
DRN
CB
IN
and the fault TIMER cycle ends, followed
) current pull-up. As the load capacitor
UV DROPS BELOW V
.
1
U
V
V
V
GATEL
UVHI
UVHST
–
UV CLEARS V
U
2
Figure 10. Undervoltage Timing (All Waveforms are Referenced to V
V
UVHI
UVHI
– V
UVHI
W
UVHST
5 A
, CHECK OV CONDITION, GATE < V
INITIAL TIMING
. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
20 • (V
20 • (V
U
V
ACL
TMRH
CB
20 • V
V
+ V
+ V
TMRL
OS
OS
OS
)
)
50 A
3 4 56
TIMER CLEARS V
GATEL
40 A + 8 • I
Undervoltage Timing
In Figure 10 when the UV pin drops below V
(time point 1), the LTC4214 shuts down with TIMER, SS
and GATE all pulling low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV recovers and clears V
initial timer cycle begins followed by a start-up cycle.
START-UP
, SENSE < V
GATE
7
50 A
8 9
DRN
10 11
TMRL
CB
, SS < 20 • V
, CHECK GATE < V
V
V
V
V
V
IN
ACL
CB
DRNCL
DRNL
– V
GATEH
5 A
OS
AND TIMER < V
GATEL
, SENSE < V
EE
)
TMRL
UVHI
5 A
CB
4214 F10
AND SS < 20 • V
(time point 2), an
UVHI
OS
– V
UVHST
421412f