LTC4214-1IMS#TRPBF Linear Technology, LTC4214-1IMS#TRPBF Datasheet - Page 15

• Manufacturer Part Number: LTC4214-1IMS#TRPBF
• Description: IC CTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4214-1IMS#TRPBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 6 V ~ 16 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
MOSFET off. To handle this situation, the TIMER dis-
charges C
SENSE voltage is less than 50mV. Therefore, any intermit-
tent overload with V
of 12.5% or more will eventually trip the circuit breaker
and shut down the LTC4214. Figure 4 shows the circuit
breaker response time in seconds normalized to 1 F for
I
C
The normalized circuit response time is estimated by
SHUTDOWN COOLING CYCLE
For the LTC4214-1 (latchoff version), TIMER latches high
with a 5 A pull-up after the circuit breaker fault TIMER
reaches 3V. For the LTC4214-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the 3V
threshold. TIMER starts with a 5 A pull-down until it
reaches the 1.7V threshold. Then, the 5 A pull-up turns
back on until TIMER reaches the 3V threshold. Four 5 A
DRN
T
is a fair gauge of MOSFET heating.
C
T
= 0 A. The asymmetric charging and discharging of
(
t
F
)
0.01
T
100
Figure 4. Circuit-Breaker Response Time
0.1
10
1
slowly with a 5 A pull-down whenever the
0
40 8
10
20 30
U
OUT
FAULT DUTY CYCLE (%)
C
T
•
( F)
t
I
< 3V and an aggregate duty cycle
DRN
3
40 50 60 70 80 90
=
U
[(40 + 8 • I
•
D
DRN
3
5
I
W
DRN
) • D – 5]
= 0 A
4214 F04
100
U
(4)
pull-down cycles and three 5 A pull-up cycles occur
between the 1.7V and 3V thresholds, creating a time
interval given by:
At the 1.7V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load. If
SS floats, an internal current source ramps SS from 0V to
1.6V in about 220 s. Connecting an external capacitor C
from SS to ground modifies the ramp to approximate an
RC response of:
An internal resistor divider (69.35k/3.65k) scales V
down by 20 times to give the analog current limit thresh-
old:
This allows the inrush current to be limited to V
The offset voltage, V
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
t
V
V
SHUTDOWN
SS
ACL
( )
t
( )
t
V
LTC4214-1/LTC4214-2
SS
V
SS
20
•
( )
7 1 3
t
1
• .
OS
5
e
V
(10mV), ensures C
OS
V C
A
R
•
SS
•
T
t
C
SS
SS
is sufficiently
ACL
15
(t)/R
421412f
SS
(5)
(6)
(7)
(t)
SS
S
.