LTC4214-1IMS#TRPBF Linear Technology, LTC4214-1IMS#TRPBF Datasheet - Page 21
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LTC4214-1IMS#TRPBF
Manufacturer Part Number
LTC4214-1IMS#TRPBF
Description
IC CTRLR HOTSWAP NEGVOLT 10MSOP
Manufacturer
Linear Technology
Type
Hot-Swap Controllerr
Datasheet
1.LTC4214-1CMS.pdf
(32 pages)
Specifications of LTC4214-1IMS#TRPBF
Applications
General Purpose
Internal Switch(s)
No
Voltage - Supply
6 V ~ 16 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APPLICATIO S I FOR ATIO
makes contact and its voltage exceeds V
the internal logic checks for OV < V
SENSE < V
conditions are met, an initial timing cycle starts and the
TIMER capacitor is charged by a 5 A current source pull-
up. At time point 3, TIMER reaches the V
and the initial timing cycle terminates. The TIMER capaci-
tor is quickly discharged. At time point 4, the V
threshold is reached and the conditions of GATE < V
SENSE < V
a GATE start-up cycle begins. SS ramps up as dictated by
R
SS
• C
GND – (–12V)
SS
; GATE is held low by the analog current limit
CB
PWRGD
CB
SENSE
TIMER
DRAIN
UV/OV
GATE
V
, SS < 20 • V
and SS < 20 • V
OUT
V
SS
IN
U
1
V
Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to V
GATEL
V
UVHI
V
LKO
U
OS
UV CLEARS V
2
OS
and TIMER < V
must be satisfied before
OVHI
W
UVHI
5 A
, CHECK OV < V
INITIAL TIMING
, GATE < V
UVHI
TMRH
. In addition,
TMRL
U
20 • (V
threshold
20 • (V
OVHI
V
GATEL
GATEL
. If all
TMRH
ACL
TMRL
CB
, GATE < V
20 • V
V
+ V
+ V
TMRL
OS
OS
OS
,
,
)
)
50 A
GATEL
3 4 56
TIMER CLEARS V
amplifier until SS crosses 20 • V
50 A sources into the external MOSFET gate and com-
pensation network. When the GATE voltage reaches the
MOSFET’s threshold, current begins flowing into the load
capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
V
current. If the SENSE voltage (V
V
activates. The TIMER capacitor, C
40 A + 8 • I
, SENSE < V
ACL
CB
START-UP
threshold at time point 7, the circuit breaker TIMER
GATE
(t) and soft-start limits the slew rate of the load
7
50 A
8 9
DRN
CB
TMRL
1011
, SS < 20 • V
LTC4214-1/LTC4214-2
, CHECK GATE < V
V
V
V
V
V
IN
ACL
CB
DRNCL
DRNL
– V
GATEH
OS
5 A
AND TIMER < V
GATEL
, SENSE < V
TMRL
OS
EE
SENSE
)
. Upon releasing GATE,
5 A
CB
T
4214 F09
AND SS < 20 • V
, is charged by a
– V
EE
) reaches the
OS
21
421412f