DS1864T+ Maxim Integrated Products, DS1864T+ Datasheet - Page 69

• Manufacturer Part Number: DS1864T+
• Description: IC LASER CTRLR 1CHAN 5.5V 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controller (Fiber Optic)r

Specifications of DS1864T+

• Number Of Channels: 1
• Voltage - Supply: 2.97 V ~ 5.5 V
• Current - Supply: 3mA
• Operating Temperature: -40°C ~ 95°C
• Package / Case: 28-WFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a start condition,
writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a stop condition. The DS1864 writes 1 to 8 bytes (1
page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
transmitting a memory address before each data byte
is sent. The address counter limits the write to one 8-
byte page (one row of the memory map). The first page
begins at address 00h and subsequent pages begin at
multiples of 8 (08h, 10h, 18h, etc). Attempts to write to
additional pages of memory without sending a stop
condition between pages results in the address counter
wrapping around to the beginning of the present row.
To prevent address wrapping from occurring, the mas-
ter must send a stop condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new start con-
dition, and write the slave address byte (R/W = 0) and
the first memory address of the next memory row
before continuing to write data.
Acknowledge Polling: Any time an EEPROM page is
written, the DS1864 requires the EEPROM write time
(t
page to EEPROM. During the EEPROM write time, the
DS1864 will not acknowledge either of its slave
addresses because it is busy. It is possible to take
advantage of that phenomenon by repeatedly address-
ing the DS1864, which allows the next page to be writ-
ten as soon as the DS1864 is ready to receive the data.
The alternative to acknowledge polling is to wait for
maximum period of t
write again to the DS1864.
EEPROM Write Cycles: When EEPROM writes occur,
the DS1864 writes the whole EEPROM memory page (8
bytes), even if only a single byte on the page was modi-
fied. Writes that do not modify all 8 bytes on the page
are allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page is
written, bytes on the page that were not modified dur-
ing the transaction are still subject to a write cycle. This
can result in a whole page being worn out over time by
writing a single byte repeatedly. Writing a page one
W
) after the stop condition to write the contents of the
W
to elapse before attempting to
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C Communication
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SFP Laser Controller and
byte at a time wears the EEPROM out eight times faster
than writing the entire page at once. The DS1864’s
EEPROM write cycles are specified in the Nonvolatile
Memory Characteristics table. The specification shown
is at the worst-case temperature. Writing to SRAM-
shadowed EEPROM memory with SEE = 1 does not
count as an EEPROM write.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation occurs
at the present value of the memory address counter. To
read a single byte from the slave, the master generates a
start condition, writes the slave address byte with R/W =
1, reads the data byte with a NACK to indicate the end of
the transfer, and generates a stop condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular address. To do this, the master
generates a start condition, writes the slave address byte
(R/W = 0), writes the memory address where it desires to
read, generates a repeated start condition, writes the
slave address byte (R/W = 1), reads data with ACK or
NACK as applicable, and generates a stop condition.
Reading Multiple Bytes from a Slave: The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master
reads the last byte it NACKs to indicate the end of the
transfer and generates a stop condition. This can be
done with or without modifying the address counter’s
location before the read cycle. The DS1864’s address
counter does not wrap on page boundaries during read
operations, but the counter will roll from its uppermost
memory address FFh to 00h if the last memory location
is read during the read transaction.
See Figure 20 for a read example using the repeated
start condition to specify the starting memory location.
To achieve best results, it is recommended that the power
supply is decoupled with a 0.01µF or a 0.1µF capacitor.
Use high-quality, ceramic, surface-mount capacitors, and
mount the capacitors as close as possible to the V
GND pins to minimize lead inductance.
SDA is an open collector output on the DS1864 that
requires a pullup resistor to realize high logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be utilized
SDA and SCL Pullup Resistors
Application Information
Power-Supply Decoupling
Diagnostic IC
CC
and
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