X9521V20I-A Intersil, X9521V20I-A Datasheet - Page 10
![IC DCP DUAL EEPROM MEM 20-TSSOP](/photos/7/36/73665/x9521v20i_sml.jpg)
X9521V20I-A
Manufacturer Part Number
X9521V20I-A
Description
IC DCP DUAL EEPROM MEM 20-TSSOP
Manufacturer
Intersil
Type
Laser Diode Controller (Fiber Optic)r
Datasheet
1.X9521V20I.pdf
(24 pages)
Specifications of X9521V20I-A
Number Of Channels
2
Voltage - Supply
2.7 V ~ 5.5 V
Current - Supply
1.5mA
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
X9521V20I-AIS
EEPROM Array Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of the
Slave Address Byte is set to one. There are three basic
read operations: Current EEPROM Address Read, Ran-
dom EEPROM Read, and Sequential EEPROM Read.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power-up, the address of the address counter is
undefined, requiring a read or write operation for initial-
ization.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an ACKNOWLEDGE and
then transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an ACKNOWLEDGE during the ninth clock and then
issues a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.
10
7 bytes
Figure 14. Current EEPROM Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
address
= 6
10
S
a
t
r
t
1 01 0 0 0 0
X9521
Address
Slave
address pointer
ends here
Addr = 7
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read opera-
tion, the master must either issue a STOP condition dur-
ing the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to
a DCP or the CONSTAT Register (i.e.: an operation
using the Device Type Identifier 1010111 or 1010010).
Immediately after an operation to a DCP or CONSTAT
Register is performed, only a “Random EEPROM Read”
is available. Immediately following a “Random EEPROM
Read” , a “Current EEPROM Address Read” or “Sequen-
tial EEPROM Read” is once again available (assuming
that no access to a DCP or CONSTAT Register occur in
the interim).
10
1
C
A
K
address
11
Data
10
5 bytes
5 bytes
S
o
p
t
address
15
10
September 21, 2010
FN8207.2