ISL97671IRZ-T Intersil, ISL97671IRZ-T Datasheet - Page 24

• Manufacturer Part Number: ISL97671IRZ-T
• Description: IC LED DVR PWM CTRL 6CH 20QFN
• Manufacturer: Intersil

Specifications of ISL97671IRZ-T

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz ~ 1.2MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 40mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

Output Channel Mask/Fault Readout
Register (0x09)
This register can be read or write; the bit position
corresponds to the channel. For example, Bit 0
corresponds to Ch0 and bit 5corresponds to Ch5 and so
on. Writing data to this register, it enables the channels
of interest. When reading data from this register, any
disabled channel and any faulted out channel will read
as 0. This allows the user to determine which channel is
Bit 7 (R/W) Bit 6 (R/W)
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
Reserved
RESERVE
REGISTER 0x08
REGISTER 0x09
BIT ASSIGNMENT
BIT ASSIGNMENT
D
DirectPWM
BITS[5-3]
VSC[1..0]
CH[5..0]
FSW
Reserved
RESERVE
D
CONFIGURATION REGISTER
OUTPUT CHANNEL REGISTER
0 (W)
Forces the PWMI signal to directly control the current
sources. Note that there is some synchronous delay between
PWMI and current sources.
These bits should always be written as 011
2 levels of Switching Frequencies (1 = 1,200kHz, 0 = 600kHz)
3 levels of Short-Circuit Thresholds (0 = disabled, 1 = 3.6V,
2 = 4.8V, 3 = 5.8V)
BIT5
24
CH5 = Channel 5, CH4 = Channel 4 and so
CH5
FIGURE 35. DESCRIPTIONS OF CONFIGURATION REGISTER
BIT FIELD DEFINITIONS
FIGURE 36. OUTPUT CHANNEL REGISTER
BIT4
1(W)
CH4
BIT FIELD DEFINITIONS
on
BIT3
1(W)
CH3
ISL97671
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
faulty and optionally not enabling it in order to allow the
rest of the system to continue to function. Additionally, a
faulted out channel can be disabled and re-enabled in
order to allow a retry for any faulty channel without
having to power-down the other channels.
The bit assignment is shown in Figure 36. The default for
Register 0x09 is 0x3F.
FSW
CH2
VSC1
CH1
VSC0
CH0
June 24, 2010
FN7631.0