ICB2FL02G Infineon Technologies, ICB2FL02G Datasheet - Page 14

• Manufacturer Part Number: ICB2FL02G
• Description: IC SMART BALLAST CONTROL DSO-19
• Manufacturer: Infineon Technologies
• Type: Ballast Controllerr

Specifications of ICB2FL02G

• Frequency: 20 ~ 120 kHz
• Current - Supply: 4.2mA
• Operating Temperature: -25°C ~ 125°C
• Package / Case: DSO-19
• Packages: PG-DSO-19
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Details
• Other names: ICB2FL02GINTR

nd
2
Generation FL-Controller for FL-Ballasts
Functional Description
In case of V
exceeds the 10.6 V level and stays below 14.1 V (Start up Hysteresis – phase 2 Figure
CC
5), the IC checks whether the lamps are assembled by detecting a current across the filaments.
The low side filaments are checked from a source current of typical I
= - 21.3 µA out of PIN 12
RES3
RES
(Figure 5 I
). This current produces a voltage drop of V
< 1.6 V (filament is ok) at the low side
RES
RES
filament sense resistor (R 36 in Figure 3), connected to GND (via low side filament). An open low side
filament is detected (see chapter 2.3.2), when the voltage at the RES PIN exceeds the V
> 1.6V
RES
threshold (Figure 5 V
).
RES
The high side filaments are checked by a current of I
> 12 µA typically via resistors R41, R42, R43
LVS
and R44 (Figure 3) into the LVS1 PIN 13 (for a single lamp operation) and LVS2 PIN 14 for a multi
lamp operation. Note: in case of a single lamp operation, the unused LVS PIN has to be disabled via
connection to GND. An open high side filament is detected (see 2.3.3) when there is no sink current
into the LVS PIN. This causes a higher source current out of the RES PIN (typical 42.6 µA / 35.4 µA)
in order to exceed V
> 1.6 V. In case of defect filaments, the IC keeps monitoring until there is an
RES
adequate current from the RES or the LVS PIN present (e.g. in case of removal a defect lamp).
When V
exceeds the 14.1 V threshold - by the end of the start up hysteresis in phase 2 Figure 5 -
CC
the IC waits for 130µs and senses the bus voltage. When the rated bus voltage is in the corridor of
12.5% < V
< 105% the IC powers up the system and enters phase 3 (Figure 5 V
> 95 %
BUSrated
BUSrated
sensing) when not, the IC initiates an UVLO when the chip supply voltage is below V
< 10.6 V. As
CC
soon as the condition for a power up is fulfilled, the IC starts the inverter gate operation with an
internal fixed Start Up frequency of 135 kHz. The PFC gate drive starts with a delay of app. 300µs.
Now, the bus voltage will be checked for a rated level above 95 % for a duration of 80 ms (phase 3
Figure 5). When leaving phase 3, the IC enters the Soft Start phase and shifts the frequency from the
internal fixed Start Up frequency of 135 kHz down to the set Preheating frequency e.g. f
= 100
RFPH
kHz.
Preliminary Datasheet
Page 14 of 55
ICB2FL02G
V1.2