ISL6622CRZ-T Intersil, ISL6622CRZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL6622CRZ-T
• Description: IC MOSFET DVR SYNC BUCK 10-DFN
• Manufacturer: Intersil

Specifications of ISL6622CRZ-T

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 1.25A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL6622CRZ-T

The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the
total gate drive power losses, the rest will be dissipated by the
external gate resistors (R
resistors (R
the typical upper and lower gate drives turn-on current paths.
.
Application Information
Layout Considerations
During switching of the devices, the parasitic inductances of
the PCB and the power devices’ packaging (both upper and
lower MOSFETs) leads to ringing, possibly in excess of the
absolute maximum rating of the devices. Careful layout can
P
P
P
R
FIGURE 7. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 6. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
DR
DR_UP
DR_LOW
EXT1
UVCC
LVCC
=
P
=
DR_UP
=
GI1
PHASE
R
=
⎛
⎜
⎝
G1
R
--------------------------------------
R
R
⎛
⎜
⎝
BOOT
and R
LO2
HI1
--------------------------------------
R
R
HI2
R
+
LO1
HI2
HI1
+
R
-------------
R
N
+
P
GI1
HI1
Q1
R
DR_LOW
R
+
GI2
HI2
EXT1
R
EXT2
) of MOSFETs. Figures 6 and 7 show
G1
+
and R
+
+
--------------------------------------- -
R
R
9
I
LO1
--------------------------------------- -
R
L2
Q
R
R
G
LO2
EXT2
L1
•
R
G
G2
VCC
+
LO1
R
C
R
R
+
LO2
) and the internal gate
GD
C
G2
R
C
EXT1
R
GD
=
G1
GS
EXT2
C
R
GS
G2
⎞
⎟
⎠
S
•
⎞
⎟
⎠
S
+
P
---------------------
•
R
-------------
Qg_Q1
N
P
---------------------
D
GI2
Q2
2
Qg_Q2
D
Q2
2
C
Q1
(EQ. 4)
DS
C
DS
ISL6622
help minimize such unwanted stress. The following advice is
meant to lead to an optimized layout:
• Keep decoupling loops (LVCC-GND and BOOT-PHASE)
• Minimize trace inductance, especially low-impedance
• Minimize the inductance of the PHASE node: ideally, the
• Minimize the input current loop: connect the source of the
In addition, for improved heat dissipation, place copper
underneath the IC whether it has an exposed pad or not. The
copper area can be extended beyond the bottom area of the
IC and/or connected to buried power ground plane(s) with
thermal vias. This combination of vias for vertical heat
escape, extended surface copper islands, and buried planes
combine to allow the IC and the power switches to achieve
their full thermal potential.
Upper MOSFET Self Turn-On Effect at Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to
self-coupling via the internal C
of the upper MOSFET could momentarily rise up to a level
greater than the threshold voltage of the device, potentially
turning on the upper switch. Therefore, if such a situation
could conceivably be encountered, it is a common practice
to place a resistor (R
the upper MOSFET to suppress the Miller coupling effect.
The value of the resistor depends mainly on the input
voltage’s rate of rise, the C
source threshold of the upper MOSFET. A higher dV/dt, a
lower C
upper FET will require a smaller resistor to diminish the
effect of the internal capacitive coupling. For most
applications, the integrated 20kΩ resistor is sufficient, not
affecting normal performance and efficiency.
The coupling effect can be roughly estimated with
Equation 5, which assumes a fixed linear input ramp and
neglects the clamping effect of the body diode of the upper
drive and the bootstrap capacitor. Other parasitic
V
R
as short as possible.
lines: all power traces (UGATE, PHASE, LGATE, GND,
LVCC) should be short and wide, as much as possible.
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source
of lower MOSFETs as possible.
GS_MILLER
=
R
DS
UGPH
/C
GS
=
+
R
dV
------- R C
dt
ratio, and a lower gate-source threshold
GI
⋅
UGPH
⋅
C
rss
rss
) across the gate and source of
GD
⎛
⎜
⎜
⎜
⎜
⎝
1 e
=
/C
–
GD
C
GS
--------------------------------- -
dV
------ - R C
GD
dt
of the MOSFET, the gate
–
⋅
ratio, as well as the gate-
V
DS
⋅
iss
C
⎞
⎟
⎟
⎟
⎟
⎠
iss
=
October 30, 2008
C
GD
(EQ. 5)
+
FN6470.2
C
GS