ISL6614CBZ Intersil, ISL6614CBZ Datasheet - Page 10

• Manufacturer Part Number: ISL6614CBZ
• Description: IC DRIVER MOSF DUAL SYNC 14SOIC
• Manufacturer: Intersil

Specifications of ISL6614CBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 10.0ns
• Current - Peak: 1.25A
• Number Of Configurations: 2
• Number Of Outputs: 4
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 10.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the SO14 package is approximately 1W at room
temperature, while the power dissipation capacity in the
QFN packages, with an exposed heat escape pad, is around
2W. See “Layout Considerations” on page 10 for thermal
transfer improvement suggestions. When designing the
driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated using Equations 2 and 3,
respectively:
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs; N
and N
respectively; PVCC is the drive voltages for both upper and
lower FETs, respectively. The I
quiescent power of the driver without capacitive load and is
typically 200mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
(R
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
P
P
R
P
P
DR_UP
DR_LOW
EXT1
DR
GI1
Qg_TOT
P
P
Qg_Q2
=
Qg_Q1
Q2
and R
I
DR
=
2 P
=
are number of upper and lower MOSFETs,
•
R
=
=
⎛
⎜
⎝
=
G1
G1
GI2
--------------------------------------
R
DR_UP
=
⎛
⎜
⎝
=
2 P
⎛
⎜
⎝
HI1
--------------------------------------
R
+
Q
----------------------------- -
and R
•
Q
-------------------------------------- - F
Q
-------------------------------------- - F
HI2
) of MOSFETs. Figures 3 and 4 show the
R
-------------
G1
R
N
G2
G1
V
+
GI1
Qg_Q1
HI1
Q1
R
GS1
R
+
V
V
+
•
•
HI2
•
GS2
EXT1
R
GS1
N
2 P
G2
PVCC
PVCC
EXT2
Q1
•
) and the internal gate resistors
+
+
DR_LOW
G1
2 P
+
Q
----------------------------- -
2
2
+
•
--------------------------------------- -
R
G2
•
10
and Q
•
LO1
--------------------------------------- -
R
V
R
Qg_Q2
LO2
Q*
GS2
EXT2
SW
•
SW
R
N
VCC product is the
+
LO1
R
+
Q2
+
R
LO2
•
GS1
•
G2
I
Q
N
EXT1
R
N
+
Q
=
⎞
⎟
⎠
•
) is defined at a
EXT2
Q2
Q1
I
•
R
and V
is the driver’s total
Q
VCC
F
G2
•
⎞
⎟
⎠
SW
VCC
•
⎞
⎟
⎠
+
P
---------------------
•
•
GS2
R
-------------
Qg_Q1
N
P
---------------------
2
GI2
Q2
Qg_Q2
2
+
2
) in the
I
Q
(EQ. 2)
(EQ. 3)
(EQ. 4)
Q1
ISL6614
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
PVCC
PHASE
R
R
BOOT
LO2
R
HI2
R
LO1
HI1
R
G2
R
G
G1
G
R
C
GI2
R
GD
C
C
GI1
GD
GS
C
GS
S
S
D
D
Q2
C
May 5, 2008
Q1
DS
C
FN9155.5
DS