SI8235BB-C-IS Silicon Laboratories Inc, SI8235BB-C-IS Datasheet - Page 12
![IC DUAL LOW SIDE DRIVER 16SOIC](/photos/7/41/74106/16-soic__7_5mmwidth__sml.jpg)
SI8235BB-C-IS
Manufacturer Part Number
SI8235BB-C-IS
Description
IC DUAL LOW SIDE DRIVER 16SOIC
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI8234BB-C-IS1.pdf
(52 pages)
Specifications of SI8235BB-C-IS
Package / Case
16-SOIC (0.300", 7.5mm Width)
Configuration
Low-Side
Input Type
Non-Inverting
Delay Time
60ns
Current - Peak
4A
Number Of Configurations
2
Number Of Outputs
2
Voltage - Supply
6.5 V ~ 24 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Number Of Channels
2
Propagation Delay Time
30 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Supply Current
2 mA
Power Dissipation
1.2 W
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High Side Voltage - Max (bootstrap)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1899-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI8235BB-C-IS
Manufacturer:
Silicon Labs
Quantity:
135
Part Number:
SI8235BB-C-IS
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si823x
Table 4. Insulation and Safety-Related Specifications
Table 5. IEC 60664-1 (VDE 0884 Part 2) Ratings
12
Parameter
Nominal Air Gap
(Clearance)
Nominal External Tracking
(Creepage)
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
Erosion Depth
Resistance
(Input-Output)
Capacitance
(Input-Output)
Input Capacitance
Notes:
Parameter
Basic Isolation Group
Installation Classification
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline:
2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1-7, 14 LD LGA)
3. Measured from input pin to ground.
16-Pin Wide Body SOIC” , “9. Package Outline: 16-Pin Narrow Body SOIC” , “11. Package Outline: 14 LD LGA
(5 x 5 mm)” , and “13. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)” . VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-16 and 8.5 mm minimum for the WB SOIC-16 package. UL does
not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and
creepage limits as 3.9 mm minimum for the NB SOIC 16 and 7.6 mm minimum for the WB SOIC-16 package.
are shorted together to form the first terminal and pins 9–16 (8-14, 14 LD LGA) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
1
1
2
2
3
Symbol
L(1O1)
L(1O2)
Material Group
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
PTI
R
C
ED
C
IO
IO
I
Test Conditions
Condition
IEC60112
f = 1 MHz
Test
Rev. 1.1
WBSOIC-16
5 kV
0.014
0.040
10
600
8.0
8.0
1.4
4.0
RMS
RMS
RMS
RMS
RMS
12
WBSOIC-16
NBSOIC-16
SOIC-16
2.5 kV
8.0/4.01
8.0/4.01
WB
0.014
0.019
I-IV
I-IV
I-III
I-III
10
600
1.4
4.0
I
12
RMS
Value
SOIC-16
2.5 kV
NB
I-IV
I-III
Specification
I-II
I-II
I
14 LD
0.014
0.021
LGA
10
600
3.5
3.5
1.4
4.0
12
RMS
14 LD
LGA
I-IV
I-III
I-II
I-II
1.5 kV
I
LGA w/
14 LD
0.014
0.021
1.75
1.75
10
Pad
600
1.4
4.0
12
RMS
w/ Pad
14 LD
LGA
I-IV
I-III
I-II
I-I
I
Unit
mm
mm
mm
mm
pF
pF
V