ISL6605IBZ Intersil, ISL6605IBZ Datasheet - Page 7

• Manufacturer Part Number: ISL6605IBZ
• Description: IC DRIVER MOSFET DUAL SYNC 8SOIC
• Manufacturer: Intersil

Specifications of ISL6605IBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 33V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -

Application Information
Fault Mode at Repetitive Startups
At a low VCC (<2V), the Thevenin equivalent of the 20k
divider at the PWM pin, as shown in the Block Diagram on
page 2, is no longer true; very high impedance will be seen
from the PWM pin to GND. Junction leakage currents from
the VCC to the resistor tub will tend to pull up the PWM input
and falsely trigger the UGATE. If the energy stored in the
bootstrap capacitor is not completely discharged during the
previous power-down period, then the upper MOSFET could
be turned on and generate a spike at the output when VCC
ramps up. A 499kΩ resistor at the PWM to GND, as shown
in Figure 3, helps bleed the leakage currents, thus
eliminating the startup spike.
Layout Considerations and MOSFET Selection
The parasitic inductances of the PCB and the power devices
(both upper and lower FETs) generate a negative ringing at
the trailing edge of the PHASE node. This negative ringing
plus the VCC adds charges to the bootstrap capacitor
through the internal bootstrap schottky diode when the
PHASE node is low. If the negative spikes are too large,
especially at high current applications with a poor layout, the
voltage on the bootstrap capacitor could exceed the VCC
and the device’s maximum rating. The V
1000
1000
900
900
800
800
700
700
600
600
500
500
400
400
300
300
200
200
100
100
0
0
FIGURE 2. POWER DISSIPATION VS. FREQUENCY
0
0
Q
Q
U
L
200 400 600 800 1000 1200 1400 1600 1800 2000
200 400 600 800 1000 1200 1400 1600 1800 2000
=200nC
=100nC
PWM
FIGURE 3. 499kΩ RESISTOR
499K
ISL6605
FREQUENCY (KHZ)
GND
Q
Q
U
L
=100nC
=50nC
7
BOOT-PHASE
Q
Q
U
L
=50nC
=50nC
Q
Q
U
L
=50nC
=20nC
ISL6605
voltage should be checked at the worst case (maximum
VCC and prior to overcurrent trip point), especially for
applications with higher than 20A per D
MOSFETs with low parasitic lead inductances, such as
multi-SOURCE leads devices (SO-8 and LFPAK), are
recommended.
Careful layout would help reduce the negative ringing peak
significantly:
A resistor placement of R
earlier design is recommended; it helps eliminate the
overcharge of the BOOT capacitor, in terms of voltage stress
across the BOOT to PHASE. When needed, 1 to 2 Ohm
R
efficiency. However, a design with good layout and using
MOSFETs with low parasitic lead inductances, such as
multi-SOURCE leads devices (SO-8 and LFPAK), is
generally not required such a resistor.
When placing the QFN part on the board, no vias or trace
should be running in between pin numbers 1 and 8 since a
small piece of copper is underneath the corner for the
orientation. In addition, connecting the thermal pad of the
QFN part to the power ground with a via, or placing a low
noise copper plane underneath the SOIC part is strongly
recommended for high switching frequency, high current
applications. This is for heat spreading and allows the part
to achieve its full thermal potential.
FIGURE 4. TYPICAL PHASE NODE VOLTAGE WAVEFORM
BOOT
- Tie the SOURCE of the upper FET and the DRAIN of
- Use the shortest low-impedance trace between the
- Tie the GND of the ISL6605 closely to the SOURCE of
the lower FET as close as possible;
SOURCE of the lower FET and the power ground;
the lower FET.
FIGURE 5. RESISTOR PLACEMENT FOR THE R
PHASE
is sufficient and has little impact on the overall
ISL6605
PHASE
BOOT
BOOT
R
BOOT
, as shown in Figure 5, in the
Negative Spike
C
2
BOOT
PAK FET.
BOOT
May 9, 2006
FN9091.7