FAN3268TMX Fairchild Semiconductor, FAN3268TMX Datasheet - Page 2

• Manufacturer Part Number: FAN3268TMX
• Description: IC BRIDGE DVR P/N-CH 2A 8SOIC
• Manufacturer: Fairchild Semiconductor

Specifications of FAN3268TMX

• Configuration: Half Bridge
• Input Type: Inverting and Non-Inverting
• Delay Time: 14ns
• Current - Peak: 3A
• Number Of Configurations: 1
• Number Of Outputs: 2
• Voltage - Supply: 4.5 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Pin Count: 8
• Mounting: Surface Mount
• Package Type: SOIC N
• Case Length: 5(Max)mm
• Case Height: 1.5(Max)mm
• Screening Level: Automotive
• Product: Half-Bridge Drivers
• Rise Time: 22 ns
• Fall Time: 17 ns
• Propagation Delay Time: 25 ns
• Supply Voltage (max): 18 V
• Supply Voltage (min): 4.5 V
• Supply Current: 1.2 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Bridge Type: Half Bridge
• Minimum Operating Temperature: - 40 C
• Output Current: 2.4 A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Compliant
• Other names: FAN3268TMXTR

© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
Ordering Information
Package Outline
Thermal Characteristics
8-Pin Small Outline Integrated Circuit (SOIC)
Notes:
1.
2.
3.
4.
5.
6.
Part Number
FAN3268TMX
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (
thermal pad) that are typically soldered to a PCB.
Theta_JT (
held at a uniform temperature by a top-side heatsink.
Theta_JA (Θ
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (
application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board
reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (
the center of the top of the package for the thermal environment defined in Note 4.


JB
JT


): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
JL
JT
JA
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
Non-Inverting Channel and Inverting
Channel + Dual Enables
Package
(1)
Figure 2. Pin Configuration (Top View)
Logic
2

40
JL
Input Threshold
(2)

TTL
31
JT
(3)

JA
89
(4)

Packing Method
JB
43
2,500 Units on
(5)
Tape & Reel

JT
3
www.fairchildsemi.com
(6)
Units
°C/W