LT1158ISW#TR Linear Technology, LT1158ISW#TR Datasheet - Page 9

• Manufacturer Part Number: LT1158ISW#TR
• Description: IC DRIVER PWR MOSFET N-CH 16SOIC
• Manufacturer: Linear Technology

Specifications of LT1158ISW#TR

• Configuration: Half Bridge
• Input Type: PWM
• Current - Peak: 500mA
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 56V
• Voltage - Supply: 5 V ~ 30 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Delay Time: -

OPERATION
goes low in PWM operation, and is maintained by the charge
pump when the top MOSFET is on DC. A regulated boost
driver at pin 1 employs a source-referenced 15V clamp
that prevents the bootstrap capacitor from overcharging
regardless of V
The LT1158 provides a current-sense comparator and fault
output circuit for protection of the top power MOSFET. The
APPLICATIONS INFORMATION
Power MOSFET Selection
Since the LT1158 inherently protects the top and bottom
MOSFETs from simultaneous conduction, there are no size
or matching constraints. Therefore selection can be made
based on the operating voltage and R
The MOSFET BV
should be increased to 3 • V
with frequent fault conditions. For the LT1158 maximum
operating supply of 30V, the MOSFET BV
from 60V to 100V.
The MOSFET R
ally chosen based on the operating effi ciency required as
long as the maximum MOSFET junction temperature is not
exceeded. The dissipation in each MOSFET is given by:
where D is the duty cycle and ∂ is the increase in R
at the anticipated MOSFET junction temperature. From this
equation the required R
For example, if the MOSFET loss is to be limited to 2W
when operating at 5A and a 90% duty cycle, the required
R
each MOSFET in the form of a normalized R
temperature curve, but ∂ = 0.007/°C can be used as an
approximation for low voltage MOSFETs. Thus if T
DS(ON)
P =D I
R
DS ON
( )
( )
would be 0.089Ω/(1 + ∂). (1 + ∂) is given for
DS
=
2
D I
DS(ON)
(
+
( )
1 ∂
DSS
DS
or output transients.
+
)
P
2
should be at least 2 • V
is specifi ed at T
R
(Refer to Functional Diagram)
(
1 ∂
DS ON
DS(ON)
+
( )
SUPPLY
)
can be derived:
in harsh environments
DS(ON)
J
= 25°C and is gener-
DSS
requirements.
SUPPLY
should be
DS(ON)
A
= 85°C
DS(ON)
, and
vs
comparator input pins 11 and 12 are normally connected
across a shunt in the source of the top power MOSFET
(or to a current-sensing MOSFET). When pin 11 is more
than 1.2V below V
offset, FAULT pin 5 begins to sink current. During a short
circuit, the feedback loop regulates V12 – V11 to 150mV,
thereby limiting the top MOSFET current.
and the available heat sinking has a thermal resistance of
20°C/W, the MOSFET junction temperature will be 125°C,
and ∂ = 0.007(125 – 25) = 0.7. This means that the required
R
which can be satisfi ed by an IRFZ34.
Note that these calculations are for the continuous operating
condition; power MOSFETs can sustain far higher dissipa-
tions during transients. Additional R
discussed under Starting High In-Rush Current Loads.
Paralleling MOSFETs
MOSFETs can be paralleled. The MOSFETs will inherently
share the currents according to their R
LT1158 top and bottom drivers can each drive four power
MOSFETs in parallel with only a small loss in switching
speeds (see Typical Performance Characteristics). Indi-
vidual gate resistors may be required to “decouple” each
MOSFET from its neighbors to prevent high frequency
oscillations—consult manufacturer’s recommendations.
DS(ON)
of the MOSFET will be 0.089Ω/1.7 = 0.0523Ω,
LT1158
Figure 1. Paralleling MOSFETs
GATE DR
GATE FB
R
+
G
: OPTIONAL 10Ω
and V12 – V11 exceeds the 110mV
R
G
DS(ON)
R
G
DS(ON)
) constraints are
LT1158
1158 F01
ratio. The
1158fb
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