ISL6596CRZ-T Intersil, ISL6596CRZ-T Datasheet
ISL6596CRZ-T
Specifications of ISL6596CRZ-T
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ISL6596CRZ-T Summary of contents
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... Pb-Free (RoHS Compliant) Ordering Information PART NUMBER PART (Note) MARKING ISL6596CBZ* 6596 CBZ ISL6596CRZ* 596Z ISL6596IBZ* 6596 IBZ ISL6596IRZ* 96IZ *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ ...
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Pinout ISL6596 (8 LD SOIC) TOP VIEW UGATE 1 BOOT 2 PWM 3 GND 4 Block Diagram VCC VCTRL PWM VCTRL = CONTROLLER VCC 2 ISL6596 8 PHASE 7 VCTRL 6 VCC 5 LGATE ISL6596 SHOOT- THROUGH 7k PROTECTION CONTROL ...
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Typical Application - Multi-Phase Converter Using ISL6596 Gate Drivers +3.3V +3.3V FB COMP VCC VSEN PWM1 PWM2 PGOOD PWM CONTROLLER (ISL69XX) ISEN1 VID (OPTIONAL) ISEN2 FS/EN GND R IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS UGPH 3 ISL6596 +5V BOOT ...
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... SOIC Package (Note DFN Package (Notes -0. (DC) Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp - 0.3V (DC BOOT BOOT Recommended Operating Conditions Ambient Temperature Range .-40°C to +100°C Maximum Operating Junction Temperature +125°C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± ...
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Electrical Specifications These specifications apply for “Recommended Operating Conditions” on page 4, unless otherwise noted. (Continued) PARAMETER LGATE Turn-On Propagation Delay Tri-state to UG/LG Rising Propagation Delay OUTPUT (Note 4) Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive ...
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Functional Pin Description Note: Pin numbers refer to the SOIC package. Check diagram for corresponding DFN pinout. UGATE (Pin 1) Upper gate drive output. Connect to gate of high-side N-Channel power MOSFET. A gate resistor is never recommended on this ...
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... MOSFETs. For optimal performance, no more than 50pF parasitic capacitive load should be present on the PWM line of ISL6596 (assuming an Intersil PWM controller is used). Bootstrap Considerations ] after the LGATE This driver features an internal bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit ...
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Power Dissipation Package power dissipation is mainly a function of the switching frequency (F ), the output drive impedance, the SW external gate resistance, and the selected MOSFET’s internal gate resistance and total gate charge. Calculating the power dissipation in ...
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Application Information MOSFET Selection The parasitic inductances of the PCB and of the power devices’ packaging (both upper and lower MOSFETs) can cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the ...
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Package Outline Drawing L10.3x3C 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 2, 09/09 3.00 6 PIN 1 INDEX AREA C B (4X) 0.10 TOP VIEW PACKAGE (10 x 0.60) OUTLINE (10x 0.25) (8x 0.50) 1.64 TYPICAL RECOMMENDED LAND PATTERN 10 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...