ISL6609ACBZ-T Intersil, ISL6609ACBZ-T Datasheet - Page 8

• Manufacturer Part Number: ISL6609ACBZ-T
• Description: IC MOSFET DRVR SYNC BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6609ACBZ-T

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 18ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -

bootstrap resistor is designed to reduce the overcharging of
the bootstrap capacitor when exposed to excessively large
negative voltage swing at the PHASE node. Typically, such
large negative excursions occur in high current applications
that use D
parasitic inductance.
The following equation helps select a proper bootstrap
capacitor size:
where Q
at V
control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q
sheet is 10nC at 4.5V (V
Q
assume a 200mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.110µF is required. The next larger standard value
capacitance is 0.22µF. A good quality ceramic capacitor is
recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
C
Q
GATE
BOOT_CAP
GATE
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
GS1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
=
is calculated to be 22nC at VCC level. We will
0.0
G1
gate-source voltage and N
Q
------------------------------ - N
20nC
2
-PAK and D-PAK MOSFETs or excessive layout
G1
is the amount of gate charge per upper MOSFET
V
≥
0.1
VOLTAGE
GS1
------------------------------------- -
ΔV
•
VCC
BOOT_CAP
Q
0.2
GATE
50nC
Q
•
GATE
SW
0.3
Q1
GS
), the output drive impedance, the
BOOT_CAP
= 100nC
ΔV
) gate-source voltage. Then the
0.4
BOOT
8
0.5
(V)
Q1
0.6
term is defined as the
is the number of
G
, from the data
0.7
0.8
ISL6609, ISL6609A
0.9
(EQ. 1)
1.0
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the
QFN package, with an exposed heat escape pad, is slightly
better. See “Layout Considerations” on page 9 for thermal
transfer improvement suggestions. When designing the
driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs; N
and N
respectively. The I
the driver without capacitive load and is typically negligible.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R
MOSFETs. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:
P
I
P
P
P
R
DR
Qg_TOT
DR
DR_UP
DR_LOW
EXT2
=
P
P
=
Q2
Qg_Q2
Qg_Q1
⎛
⎜
⎝
P
Q
----------------------------------------------------- -
=
DR_UP
=
are number of upper and lower MOSFETs,
G1
=
R
=
⎛
⎜
⎝
G1
G1
P
--------------------------------------
R
•
⎛
⎜
⎝
Qg_Q1
=
=
UVCC N
HI1
--------------------------------------
R
V
+
and R
HI2
Q
---------------------------------- F
GS1
Q
---------------------------------- F
+
R
-------------
R
N
+
G2
G1
P
GI1
HI1
R
Q1
Q
DR_LOW
R
+
V
V
HI2
+
•
GS2
V
EXT1
•
•
R
GS1
G2
P
VCC
CC
VCC
EXT2
Qg_Q2
Q1
, should be a short to avoid
product is the quiescent power of
G1
+
2
+
2
+
+
--------------------------------------- -
R
•
•
Q
---------------------------------------------------- -
and Q
I
LO1
--------------------------------------- -
R
R
+
Q
G2
LO2
SW
SW
EXT2
I
•
Q
R
•
VCC
+
LO1
R
•
•
LVCC N
•
V
R
+
LO2
VCC
G2
GS1
N
N
GS2
EXT1
R
Q
=
Q2
Q1
) is defined at a
EXT2
R
and V
is the driver’s total
G2
•
⎞
⎟
⎠
GI1
•
⎞
⎟
⎠
+
Q2
P
---------------------
•
GS2
R
-------------
N
Qg_Q1
P
---------------------
and R
⎞
⎟
⎠
GI2
Qg_Q2
Q2
2
•
2
F
) in the
SW
April 27, 2009
GI2
FN9221.2
(EQ. 2)
+
(EQ. 3)
(EQ. 4)
Q1
) of
I
Q