ISL2110ABZ Intersil, ISL2110ABZ Datasheet
ISL2110ABZ
Specifications of ISL2110ABZ
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ISL2110ABZ Summary of contents
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... PART TEMP NUMBER PART RANGE (Note) MARKING (°C) ISL2110ABZ* 2110 ABZ -40 to +125 8 Ld SOIC ISL2110AR4Z* 211 0AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A ISL2111ABZ* 2111 ABZ -40 to +125 8 Ld SOIC ISL2111AR4Z* 211 1AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A ISL2111ARTZ* 211 1ARTZ -40 to +125 10 Ld 4x4 TDFN L10.4x4 *Add “ ...
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Pinouts ISL2111 (10 LD 4X4 TDFN) TOP VIEW VDD Application Block Diagram PWM CONTROLLER 2 ISL2110, ISL2111 VSS ISL2110, ISL2111 (8 LD ...
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Functional Block Diagram ISL2111 ISL2111 *EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane. +12V PWM +12V ...
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... Max Power Dissipation at +25°C in Free Air 8 Ld SOIC (Note 1. TDFN (Notes 3. DFN (Notes 3.1W Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to +150°C Junction Temperature Range .-55°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp - 100V 12V 0V, No Load HO, Unless Otherwise Specified. ...
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Electrical Specifications PARAMETERS SYMBOL UNDERVOLTAGE PROTECTION V Rising Threshold Threshold Hysteresis Rising Threshold V HB Threshold Hysteresis V BOOT STRAP DIODE Low Current Forward Voltage High Current Forward Voltage Dynamic ...
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Pin Descriptions SYMBOL V Positive supply to lower gate driver. Bypass this pin High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. HO High-side ...
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Typical Performance Curves 10 -40°C 1 +25°C 0 +125°C 0.01 10k 100k FREQUENCY (Hz) FIGURE 7. I OPERATING CURRENT vs FREQUENCY HB 300 14V DD HB 250 200 150 100 ...
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Typical Performance Curves LPLH HPLH HPHL 25 - TEMPERATURE (°C) FIGURE 13. ISL2110 PROPAGATION DELAYS vs TEMPERATURE 8.0 7.5 t MON 7.0 6.5 6.0 5.5 5.0 4.5 4.0 -50 ...
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Typical Performance Curves 120 110 I DD 100 ( FIGURE 19. ISL2110 QUIESCENT CURRENT vs VOLTAGE 1.00 0.10 0. ...
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Package Outline Drawing L10.4x4 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 1/08 4. 4.00 TOP VIEW ( 3. 3.80 TYPICAL RECOMMENDED LAND PATTERN 10 ISL2110, ISL2111 PIN ...
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... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for the L dimension TERMINAL TIP MILLIMETERS ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...