ISL89411IBZ Intersil, ISL89411IBZ Datasheet - Page 8

• Manufacturer Part Number: ISL89411IBZ
• Description: IC DRVR MOSFET DUAL-CH 8-SOIC
• Manufacturer: Intersil

Specifications of ISL89411IBZ

• Configuration: High and Low Side, Synchronous
• Input Type: Inverting
• Delay Time: 18ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• Voltage - Supply: 4.5 V ~ 18 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -

.subckt comp1 out inp inm vss
e1 out vss table { (v(inp) v(inm))* 5000} (0,0) (3.2,3.2)
Rout out vss 10meg
Rinp inp vss 10meg
Rinm inm vss 10meg
.ends comp1
Application Guidelines
It is important to minimize inductance to the power FET by
keeping the output drive current loop as short as possible.
Also, the decoupling capacitor, Cq, should be a high quality
ceramic capacitor with a Q that should be a least 10x the
gate Q of the power FET. A ground plane under this circuit is
also recommended.
In applications where it is difficult to place the driver very
close to the power FET (which may result with excessive
parasitic inductance), it then may be necessary to add an
external gate resistor to dampen the inductive ring. If this
resistor must be too large in value to be effective, then as an
alternative, Schottky diodes can be added to clamp the ring
voltage to V+ or GND.
FIGURE 14. RECOMMENDED LAYOUT METHODS
C
q
GND
V+
C
POSSIBLE TO THE V+ AND
GND PINS
q
8
SHOULD BE AS CLOSE AS
SHORT AS
POSSIBLE
LOOP AS
ISL89410, ISL89411, ISL89412
Where high supply voltage operation is required (15V to
18V), input signals with a minimum of 3.3V input drive is
suggested and a minimum rise/fall time of 100ns. This is
recommended to minimize the internal bias current power
dissipation.
Excessive power dissipation in the driver can result when
driving highly capacitive FET gates at high frequencies.
These gate power losses are defined by Equation 1:
where:
P = Power
Q
V
f
Adding a gate resistor to the output of the driver will transfer
some of the driver dissipation to the resistor. Another
possible solution is to lower the gate driver voltage which
also lowers Q
P
SW
gs
FIGURE 15. SUGGESTED CONFIGURATION FOR DRIVING
c
=
= Charge of the Power FET at V
= Gate drive voltage (V+)
= switching Frequency
2 Q
•
C
•
C
V
INDUCTIVE LOADS
q
c
gs
.
GND
•
f
SW
V+
PARASITIC LEAD
INDUCTANCE
gs
July 1, 2009
FN6798.1
(EQ. 1)